Peter J Gruber

US Patent:

6534863, Mar 18, 2003

Filed:

Feb 9, 2001

Appl. No.:

09/781121

Inventors:

George F. Walker - New York NY
Ronald D. Goldblatt - Yorktown Heights NY
Peter A. Gruber - Mohegan Lake NY
Raymond R. Horton - Dover Plains NY
Kevin S. Petrarca - Newburgh NY
Richard P. Volant - New Fairfield CT
Tien-Jen Cheng - Bedford NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257737, 257751, 257761, 257762, 257766, 257769, 257781, 257784

Abstract:

A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

US Patent:

20030092254, May 15, 2003

Filed:

Dec 18, 2002

Appl. No.:

10/322831

Inventors:

George Walker - New York NY, US
Ronald Goldblatt - Yorktown Heights NY, US
Peter Gruber - Mohegan Lake NY, US
Raymond Horton - Dover Plains NY, US
Kevin Petrarca - Newburgh NY, US
Richard Volant - New Fairfield CT, US
Tien-Jen Cheng - Bedford NY, US

International Classification:

H01L021/44

US Classification:

438/613000

Abstract:

A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

US Patent:

20090001248, Jan 1, 2009

Filed:

Aug 23, 2007

Appl. No.:

11/844070

Inventors:

Matthew J. Farinelli - Bronx NY, US
Steven Cordes - Yorktown Heights NY, US
Donna S. Nielsen - Yorktown Heights NY, US
Samuel Roy McKnight - New Paltz NY, US
Jay S. Chey - Ossining NY, US
Peter A. Gruber - Mohegan Lake NY, US
Joanna Rosner - Cortland Manor NY, US

International Classification:

B22C 9/00

US Classification:

249119

Abstract:

A solder mold includes a substrate and a plurality of cavities for holding solder to be transferred to an integrated circuit. The plurality of cavities comprises cavities of at least two different volumes.

US Patent:

20090004840, Jan 1, 2009

Filed:

Jun 27, 2007

Appl. No.:

11/769389

Inventors:

Matthew J. Farinelli - Bronx NY, US
Steven Cordes - Yorktown Heights NY, US
Donna S. Nielsen - Yorktown Heights NY, US
Samuel Roy McKnight - New Paltz NY, US
Jay S. Chey - Ossining NY, US
Peter A. Gruber - Mohegan Lake NY, US
Joanna Rosner - Cortlandt Manor NY, US

International Classification:

H01L 21/441
H01B 13/00

US Classification:

438616, 216 18, 257E21476

Abstract:

A method for fabricating a solder transfer mold includes masking a substrate with a masking agent. A pattern is transferred to the substrate mask. The masked substrate is etched until cavities of a first volume are formed. The cavities of the first volume are selectively coated. The masked substrate is etched until cavities of a second volume are formed.

US Patent:

20120234902, Sep 20, 2012

Filed:

Jun 4, 2012

Appl. No.:

13/487378

Inventors:

S. Jay Chey - Hartsdale NY, US
David Danovitch - Canton de Granby, CA
Peter A. Gruber - Mohegan Lake NY, US
Cornelia K. Tsang - Mohegan Lake NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

B23K 31/02
B23K 3/06

US Classification:

228260, 228 33

Abstract:

A plurality of through-substrate holes is formed in each of at least one substrate. Each through-substrate hole extends from a top surface of the at least one substrate to the bottom surface of the at least one substrate. The at least one substrate is held by a stationary chuck or a rotating chuck. Vacuum suction is provided to a set of through-substrate holes among the plurality of through-substrate holes through a vacuum manifold attached to the bottom surface of the at least one substrate. An injection mold solder head located above the top surface of the at least one substrate injects a solder material into the set of through-substrate holes to form a plurality of through-substrate solders that extend from the top surface to the bottom surface of the at least one substrate. The vacuum suction prevents formation of air bubbles or incomplete filling in the plurality of through-substrate holes.

US Patent:

20140339179, Nov 20, 2014

Filed:

Aug 5, 2014

Appl. No.:

14/451781

Inventors:

- San Rafael CA, US
Peter Edward Gruber - San Rafael CA, US
Nathaniel Taylor Coleman - San Rafael CA, US

International Classification:

H01L 31/048
H01L 31/042

US Classification:

211 411

Abstract:

A photovoltaic module frame having hollow sections into which male ends of a corner key are received such that two frame sections can be connected together in orthogonal directions. The male ends of the corner key may have teeth thereon. Once so engaged, a tool head may be applied to the corner formed by the adjacent frame sections. The tool head may create indentations in the profiles that engage the teeth of the corner keys within the frame sections, thereby forming a corner of a module frame.

US Patent:

20140102997, Apr 17, 2014

Filed:

Dec 13, 2013

Appl. No.:

14/106189

Inventors:

John Raymond West - San Rafael CA, US
Peter Edward Gruber - San Rafael CA, US
Nathaniel Taylor Coleman - San Rafael CA, US

Assignee:

ZEP SOLAR, INC. - San Rafael CA

International Classification:

H01L 31/042
H01L 31/18

US Classification:

211 411, 29428

Abstract:

The invention comprises components and a method for producing components that, without limitation, frame a photovoltaic (“PV”) module such that the frame (i) provides improved stability for the groove incorporated therein, (ii) enables a higher percentage of in-tolerance final PV module product, and (iii) enables acceptance of a wider tolerance range in raw frame extrusion than the prior art. An embodiment may include a profile with a first hollow and a second hollow, collinear to one another and separated by a diagonal component. A corner key with teeth and male portions may engage the first hollow of adjacent profiles that meet orthogonally. Once so engaged, a tool head may be applied to the corner formed by the adjacent profiles. The application of the tool head may create indentations in the profiles that engage the teeth of the corner keys within the profiles, forming a corner of a PV module frame.