Prashant Sethi from 132 Blue Heron Dr, Wexford, PA 15090, age 53, Phone: 7247998356

Resumes

Senior Director, Head Of Software Test Engineering

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Location:

132 Blue Heron Dr, Wexford, PA 15090

Industry:

Hospital & Health Care

Work:

Highmark Health
Senior Director, Head of Software Test Engineering
Cognizant Technology Solutions Jun 2008 - Aug 2018
Senior Director Healthcare Practice
Wipro Technologies Jul 2007 - Jun 2008
Delivery Manager, Communications and Technology Practice
Infosys Aug 1999 - Jun 2007
Senior Project Manager, Telecommunications Practice
Cmc Ltd Jan 1995 - Jul 1999
Senior Developer

Education:

Institute of Management Technology, Ghaziabad 1997 - 2000
Master of Business Administration, Masters, Finance Department of Technology, Savitribai Phule Pune University 1990 - 1994
Bachelor of Engineering, Bachelors, Electronics Pune University
Bachelor of Engineering, Bachelors

Skills:

Program Management
Pre Sales
Global Delivery
Software Project Management
Offshoring

Prashant Sethi

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Us Patents

Sequencer Address Management
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US Patent:

7743233, Jun 22, 2010
Filed:

Apr 5, 2005
Appl. No.:

11/100032
Inventors:

Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Richard A. Hankins - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Jason W. Brandt - Austin TX, US
Prashant Sethi - Folsom CA, US
Douglas M. Carmean - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Ryan N. Rakvic - Palo Alto CA, US
John L. Reid - Portland OR, US
David K. Poulsen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
James Paul Held - Portland OR, US
James Charles Abel - Phoenix AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/00
US Classification:

712220
Abstract:

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Mechanism For Monitoring Instruction Set Based Thread Execution On A Plurality Of Instruction Sequencers
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US Patent:

8010969, Aug 30, 2011
Filed:

Jun 13, 2005
Appl. No.:

11/151809
Inventors:

Richard A. Hankins - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Hong Wang - Fremont CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Trung A. Diep - San Jose CA, US
Xiang Zou - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Paul M. Petersen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
Ryan N. Rakvic - Palo Alto CA, US
Prashant Sethi - Folsom CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 3/00
G06F 9/46
G06F 7/38
US Classification:

719318, 718100, 712235
Abstract:

A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Mechanism To Schedule Threads On Os-Sequestered Sequencers Without Operating System Intervention
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US Patent:

8607235, Dec 10, 2013
Filed:

Dec 30, 2004
Appl. No.:

11/027445
Inventors:

Richard A. Hankins - San Jose CA, US
Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Trung A. Diep - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Asit K. Mallick - Santa Clara CA, US
Baiju V. Patel - Portland OR, US
James Paul Held - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Prashant Sethi - Folsom CA, US
Xinmin Tian - San Jose CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/46
US Classification:

718102
Abstract:

Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Mechanism For Instruction Set Based Thread Execution On A Plurality Of Instruction Sequencers
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US Patent:

20070006231, Jan 4, 2007
Filed:

Jun 30, 2005
Appl. No.:

11/173326
Inventors:

Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Ed Grochowski - San Jose CA, US
James Held - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan Kaushik - Portland OR, US
Gautham Chinya - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggarwal - Portland OR, US
Scott Rodgers - Hillsboro OR, US
Prashant Sethi - Folsom CA, US
Baiju Patel - Portland OR, US
Richard Hankins - San Jose CA, US
International Classification:

G06F 9/46
US Classification:

718100000
Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism For Monitoring Instruction Set Based Thread Execution On A Plurality Of Instruction Sequencers
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US Patent:

20120017221, Jan 19, 2012
Filed:

Jul 26, 2011
Appl. No.:

13/191317
Inventors:

Richard A. Hankins - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Hong Wang - Fremont CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Trung A. Diep - San Jose CA, US
Xiang Zou - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Paul M. Petersen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
Ryan N. Rakvic - Palo Alto CA, US
Prashant Sethi - Folsom CA, US
International Classification:

G06F 9/46
US Classification:

719318, 718102
Abstract:

A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Mechanism For Instruction Set Based Thread Execution On A Plurality Of Instruction Sequencers
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US Patent:

20130054940, Feb 28, 2013
Filed:

Sep 10, 2012
Appl. No.:

13/608970
Inventors:

Hong Wang - Fremont CA, US
John Shen - San Jose CA, US
Ed Grochowski - San Jose CA, US
James Paul Held - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan D. Kaushik - Portland OR, US
Gautham Chinya - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggarwal - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Prashant Sethi - Folsom CA, US
Baiju V. Patel - Portland OR, US
Richard Andrew Hankins - San Jose CA, US
International Classification:

G06F 9/312
US Classification:

712205, 712E09033
Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism For Instruction Set Based Thread Execution Of A Plurality Of Instruction Sequencers
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US Patent:

20130219399, Aug 22, 2013
Filed:

Mar 15, 2013
Appl. No.:

13/843164
Inventors:

Hong Wang - Santa Clara CA, US
John Shen - San Jose CA, US
Edward Grochowski - San Jose CA, US
Richard Hankins - Santa Clara CA, US
Gautham Chinya - Hillsboro OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivnandan Kaushik - Portland OR, US
Xiang Chris Zou - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Scott Dion Rodgers - Hillsboro OR, US
Xinmin Tian - Union City CA, US
Anil Aggawal - Portland OR, US
Prashant Sethi - Folsom CA, US
Baiju Patel - Portland OR, US
James Held - Portland OR, US
International Classification:

G06F 9/48
US Classification:

718102
Abstract:

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Apparatus, System, And Method For Persistent User-Level Thread
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US Patent:

20170102944, Apr 13, 2017
Filed:

Dec 21, 2016
Appl. No.:

15/386615
Inventors:

- Santa Clara CA, US
Hong Wang - Santa Clara CA, US
Prashant Sethi - Folsom CA, US
Shivnandan Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Richard Hankins - San Jose CA, US
Xiang Zou - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Jason W. Brandt - Austin TX, US
Anil Aggarwal - Portland OR, US
John L. Reid - Portland OR, US
International Classification:

G06F 9/30
G06F 9/38
G06F 9/46
Abstract:

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.