Rahim Te Kavari

US Patent:

6548343, Apr 15, 2003

Filed:

Oct 31, 2000

Appl. No.:

09/702985

Inventors:

Scott R. Summerfelt - Cupertino CA
Theodore S. Moise - Los Altos CA
Guoqiang Xing - Plano TX
Luigi Colombo - Dallas TX
Tomoyuki Sakoda - San Jose CA
Stephen R. Gilbert - San Francisco CA
Alvin L. S. Loke - Singapore, SG
Shawming Ma - Sunnyvale CA
Rahim Kavari - Campbell CA
Jun Amano - Hillsborough CA

Assignee:

Agilent Technologies Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218242

US Classification:

438240, 438 3, 438250, 438393

Abstract:

An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure ( of FIG. ), the bottom electrode having a top surface and sides; forming a capacitor dielectric ( of FIG. ) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode ( and of FIG. ) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer ( and of FIG. ) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

US Patent:

20020006674, Jan 17, 2002

Filed:

Dec 19, 2000

Appl. No.:

09/741650

Inventors:

Shawming Ma - Sunnyvale CA, US
Guoqiang Xing - Plano TX, US
Rahim Kavari - Campbell CA, US
Scott Summerfelt - Cupertino CA, US
Tomoyuki Sakoda - San Jose CA, US

International Classification:

H01L021/00
H01L021/8242
H01L021/44

US Classification:

438/003000, 438/256000, 438/239000, 438/597000

Abstract:

An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (and of FIG. ) of a ferroelectric capacitor comprised of a bottom electrode (of FIG. ) situated under the top electrode and a ferroelectric material (of FIG. ) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (or of FIG. ) over the top electrode; forming an opening (of FIG. ) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (of FIG. ) in the opening to form an electrical connection with the top electrode.

US Patent:

20080131655, Jun 5, 2008

Filed:

May 15, 2007

Appl. No.:

11/749128

Inventors:

Barbara Wacker - Saratoga CA, US
Ephraim Suhir - Los Altos CA, US
Subrata Dey - Fremont CA, US
Peter Schwartz - Livermore CA, US
Rahim Kavari - Campbell CA, US

International Classification:

B32B 7/00

US Classification:

428119

Abstract:

Carbon nanotube-based structures and methods for removing heat from solid-state devices are disclosed. In one embodiment, a copper substrate has thermal interface materials on top of front and back surfaces of the copper substrate. Each thermal interface material (TIM) comprises a layer of carbon nanotubes and a filler material located between the carbon nanotubes. The summation of the thermal resistance of the copper substrate, the bulk thermal resistance of each TIM, the contact resistance between each TIM and the copper substrate, the contact resistance between one TIM and a solid-state device, and the contact resistance between the other TIM and a heat conducting surface has a value of 0.06 cmK/W or less.

US Patent:

20120125256, May 24, 2012

Filed:

Aug 13, 2011

Appl. No.:

13/209390

Inventors:

Karl-Josef Kramer - San Jose CA, US
Mehrdad M. Moslehi - Los Altos CA, US
David Xuan-Qi Wang - Fremont CA, US
Subramanian Tamilmani - Milpitas CA, US
Sam Tone Tor - Pleasanton CA, US
Rahim Kavari - Campbell CA, US
Rafael Ricolcol - Fremont CA, US
George Kamian - Scotts Valley CA, US
Joseph Leigh - Santa Clara CA, US

Assignee:

SOLEXEL, INC. - Milpitas CA

International Classification:

C30B 25/02

US Classification:

117 95

Abstract:

Mechanisms are disclosed by which a semiconductor wafer, silicon in some embodiments, is repeatedly used to serve as a template and carrier for fabricating high efficiency capable thin semiconductor solar cells substrates. Mechanisms that enable such repeated use of these templates at consistent quality and with high yield are disclosed.

US Patent:

20120167819, Jul 5, 2012

Filed:

Dec 31, 2011

Appl. No.:

13/341976

Inventors:

Karl-Josef Kramer - San Jose CA, US
Mehrdad M. Moslehi - Los Altos CA, US
David Xuan-Qi Wang - Fremont CA, US
Rahim Kavari - Campbell CA, US
Rafael Ricolcol - Hayward CA, US
Jay Ashjaee - Cupertino CA, US

Assignee:

SOLEXEL, INC. - Milpitas CA

International Classification:

C30B 25/18

US Classification:

117 95, 117 97

Abstract:

The disclosed subject matter pertains to deposition of thin film or thin foil materials in general, but more specifically to deposition of epitaxial monocrystalline or quasi-monocrystalline silicon film (epi film) for use in manufacturing of high efficiency solar cells. In operation, methods are disclosed which extend the reusable life and to reduce the amortized cost of a substrate or template used in the manufacturing process of silicon solar cells. Further, methods are disclosed which provide for the conversion of a low quality starting surface into an improved quality starting surface of a silicon wafer.