Christopher J. Hughes - Cupertino CA, US Mayank Bomb - Hillsboro OR, US Jason W. Brandt - Austin TX, US Mark J. Buxton - Chandler AZ, US Mark J. Charney - Lexington MA, US Srinivas Chennupaty - Portland OR, US Jesus Corbal - Barcelona, ES Martin G. Dixon - Portland OR, US Milind B. Girkar - Sunnyvale CA, US Jonathan C. Hall - Hillsboro OR, US Hideki (Saito) Ido - Sunnyvale CA, US Peter Lachner - Heroldstatt, DE Gilbert Neiger - Portland OR, US Chris J. Newburn - South Beloit IL, US Rajesh S. Parthasarathy - Hillsboro OR, US Bret L. Toll - Hillsboro OR, US Robert Valentine - Kiryat Tivon, IL Jeffrey G. Wiedemeier - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/38 G06F 9/00 G06F 9/44 G06F 15/00
US Classification:
712244
Abstract:
According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
Instruction And Logic For Performing A Dot-Product Operation
Ronen Zohar - Sunnyvale CA, US Mark Seconi - Beaverton OR, US Rajesh Parthasarathy - Hillsboro OR, US Srinivas Chennupaty - Portland OR, US Mark Buxton - Chandler AZ, US Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 7/52
US Classification:
708626
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
Instruction And Logic For Performing A Dot-Product Operation
Ronen Zohar - Sunnyvale CA, US Mark Seconi - Beaverton OR, US Rajesh Parthasarathy - Hillsboro OR, US Srinivas Chennupaty - Portland OR, US Mark Buxton - Chandler AZ, US Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 7/48
US Classification:
708490
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
Instruction And Logic For Performing A Dot-Product Operation
Ronen Zohar - Sunnyvale CA, US Mark Seconi - Beaverton OR, US Rajesh Parthasarathy - Hillsboro OR, US Srinivas Chennupaty - Portland OR, US Mark Buxton - Chandler AZ, US Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 17/10
US Classification:
708495
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
Instruction And Logic For Performing A Dot-Product Operation
Ronen Zohar - Sunnyvale CA, US Mark Seconi - Beaverton OR, US Rajesh Parthasarathy - Hillsboro OR, US Srinivas Chennupaty - Portland OR, US Mark Buxton - Chandler AZ, US Chuck Desylva - Fair Oaks CA, US
International Classification:
G06F 9/30
US Classification:
712207
Abstract:
Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
Providing State Storage In A Processor For System Management Mode
Mahesh Natu - Sunnyvale CA, US Thanunathan Rangarajan - Bangalore, IN Gautam Doshi - Bangalore, IN Shamanna M. Datta - Hillsboro OR, US Baskaran Ganesan - Bangalore, IN Mohan J. Kumar - Aloha OR, US Rajesh S. Parthasarathy - Hillsboro OR, US Frank Binns - Portland OR, US Rajesh Nagaraja Murthy - Bangalore, IN Robert C. Swanson - Olympia WA, US
International Classification:
G11C 7/10
US Classification:
711105
Abstract:
In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
- Santa Clara CA, US Yen-Kuang (Y.K.) Chen - Cupertino CA, US Mayank Bomb - Hillsboro OR, US Jason W. Brandt - Austin TX, US Mark J. Buxton - Chandler AZ, US Mark J. Charney - Lexington MA, US Srinivas Chennupaty - Portland OR, US Jesus Corbal - Barcelona, ES Martin G. Dixon - Portland OR, US Milind B. Girkar - Sunnyvale CA, US Jonathan C. Hall - Hillsboro OR, US Hideki (Saito) Ido - Sunnyvale CA, US Peter Lachner - Heroldstatt, DE Gilbert Neiger - Portland OR, US Chris J. Newburn - South Beloit IL, US Rajesh S. Parthasarathy - Hillsboro OR, US Bret L. Toll - Hillsboro OR, US Robert Valentine - Qiryat Tivon, IL Jeffrey G. Wiedemeier - Austin TX, US
International Classification:
G06F 9/38 G06F 9/30
Abstract:
According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
Christopher J. Hughes - Santa Clara CA, US Yen-Kuang (Y.K.) Chen - Palo Alto CA, US Mayank Bomb - Hillsboro OR, US Jason W. Brandt - Austin TX, US Mark J. Buxton - Chandler AZ, US Mark J. Charney - Lexington MA, US Srinivas Chennupaty - Portland OR, US Jesus Corbal - King City OR, US Martin G. Dixon - Portland OR, US Milind B. Girkar - Sunnyvale CA, US Jonathan C. Hall - Hillsboro OR, US Hideki (Saito) Ido - Sunnyvale CA, US Peter Lachner - Heroldstatt, DE Gilbert Neiger - Portland OR, US Chris J. Newburn - South Beloit IL, US Rajesh S. Parthasarathy - Hillsboro OR, US Bret L. Toll - Hillsboro OR, US Robert Valentine - Kiryat Trvon, IL Jeffrey G. Wiedemeier - Austin TX, US
International Classification:
G06F 9/38 G06F 9/30
Abstract:
According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.