Rajinder K Singh

US Patent:

7330936, Feb 12, 2008

Filed:

Apr 19, 2005

Appl. No.:

11/109163

Inventors:

Thang M. Tran - Austin TX, US
Muralidharan S. Chinnakonda - Austin TX, US
Rajinder P. Singh - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/08

US Classification:

711128, 711208

Abstract:

A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.

US Patent:

7918492, Apr 5, 2011

Filed:

Jan 5, 2009

Appl. No.:

12/348566

Inventors:

Adrian Nicholas Alexander Elliott - Dearborn MI, US
Justin Thales Johnson - Idaho Falls ID, US
Jason Falenski - Berkley MI, US
Rajinder P. Singh - Plymouth MI, US
Dave Michael Lechkun - Shelby Township MI, US

Assignee:

Ford Global Technologies, LLC - Dearborn MI

International Classification:

B60J 5/04

US Classification:

29614612

Abstract:

A vehicle door articulating mechanism including an articulating hinge assembly having a hinge arm pivotally mounted to a vehicle structure at one end thereof, a vehicle door pivotally mounted via first and second hinge mounts to the hinge arm at an opposite end of the hinge arm, a first cam mounted to the first hinge mount at one end of the hinge arm, a second cam mounted to the second hinge mount at an opposite end of the hinge arm, and a belt encircling both first and second cams. The hinge arm is disposed at first and second angular positions when the vehicle door is respectively disposed in closed and opened positions. The vehicle door articulating mechanism allows the door to articulate away independent of an adjacent vehicle door during initial and continued opening of vehicle door.

US Patent:

8069614, Dec 6, 2011

Filed:

Apr 22, 2005

Appl. No.:

11/578171

Inventors:

Richard Borsos - Plymouth MI, US
Sergio E. Romero - Beverly Hills MI, US
Rajinder P. Singh - Plymouth MI, US

Assignee:

Ford Global Technologies, LLC - Dearborn MI
Toyoda Gosei Co., Ltd. - Aichi

International Classification:

E06B 7/22

US Classification:

494981, 494951

Abstract:

The present invention relates to an improved retention sealing strip () that improves the ease of assembly, and reduces manufacturing costs. The sealing strip () includes a retention section () having an upper hub (), a first retention leg () positioned forward of the upper hub (), a second retention leg () rearward (e. g. , positioned at an inner-side of a vehicle cabin) of the first retention leg (), an upper recess () positioned rearward of the upper hub (), and a lower recess () positioned between the first and second retention legs ( respectively). The sealing strip () also includes a sealing section () integrally formed with the retention section ().

US Patent:

20060200649, Sep 7, 2006

Filed:

Feb 17, 2005

Appl. No.:

11/060142

Inventors:

Rajinder Singh - Austin TX, US
Muralidharan Chinnakonda - Austin TX, US
Bhasi Kaithamana - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 13/38
G06F 15/00

US Classification:

712220000, 710062000

Abstract:

A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a second logic substantially coupled in parallel with the first logic, and performing a sign extension on the data bus using the second logic.

US Patent:

62792679, Aug 28, 2001

Filed:

Aug 11, 1999

Appl. No.:

9/372082

Inventors:

Eric William Barrett - Milford MI
Robert Edward Kosior - Livonia MI
Rajinder Pal Singh - Plymouth MI

Assignee:

Ford Global Tech., Inc. - Dearborn MI

International Classification:

E05D 1510

US Classification:

49224

Abstract:

An assembly for use with a vehicle sliding door 12 which includes a first wheel 24, which is movably disposed within a first track 40 located on the vehicle and having a ramped portion 44, and a second wheel 32 which is movably disposed within a second track 60. The assembly includes a brake pad 62, which is disposed within the second track 60, which frictionally engages the second wheel 32, and which cooperates with the ramped portion 44 to hold door 12 in an open position.

US Patent:

60413905, Mar 21, 2000

Filed:

Dec 23, 1996

Appl. No.:

8/773545

Inventors:

Peichun Peter Liu - Austin TX
Rajinder Paul Singh - Austin TX
Shih-Hsiung Steve Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1212

US Classification:

711110

Abstract:

A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

US Patent:

57874786, Jul 28, 1998

Filed:

Mar 5, 1997

Appl. No.:

8/810775

Inventors:

Dwain Alan Hicks - Pflugerville TX
Peichun Peter Liu - Austin TX
Michael John Mayfield - Austin TX
Rajinder Paul Singh - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141

Abstract:

A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

US Patent:

63049392, Oct 16, 2001

Filed:

Sep 23, 1999

Appl. No.:

9/404036

Inventors:

Peichun Peter Liu - Austin TX
Rajinder Paul Singh - Austin TX
Shih-Hsiung Steve Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1212

US Classification:

711110

Abstract:

A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.