Rajinder Paul Singh

US Patent:

7330936, Feb 12, 2008

Filed:

Apr 19, 2005

Appl. No.:

11/109163

Inventors:

Thang M. Tran - Austin TX, US
Muralidharan S. Chinnakonda - Austin TX, US
Rajinder P. Singh - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/08

US Classification:

711128, 711208

Abstract:

A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.

US Patent:

20060200649, Sep 7, 2006

Filed:

Feb 17, 2005

Appl. No.:

11/060142

Inventors:

Rajinder Singh - Austin TX, US
Muralidharan Chinnakonda - Austin TX, US
Bhasi Kaithamana - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 13/38
G06F 15/00

US Classification:

712220000, 710062000

Abstract:

A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a second logic substantially coupled in parallel with the first logic, and performing a sign extension on the data bus using the second logic.

US Patent:

60413905, Mar 21, 2000

Filed:

Dec 23, 1996

Appl. No.:

8/773545

Inventors:

Peichun Peter Liu - Austin TX
Rajinder Paul Singh - Austin TX
Shih-Hsiung Steve Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1212

US Classification:

711110

Abstract:

A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

US Patent:

57874786, Jul 28, 1998

Filed:

Mar 5, 1997

Appl. No.:

8/810775

Inventors:

Dwain Alan Hicks - Pflugerville TX
Peichun Peter Liu - Austin TX
Michael John Mayfield - Austin TX
Rajinder Paul Singh - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141

Abstract:

A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

US Patent:

63049392, Oct 16, 2001

Filed:

Sep 23, 1999

Appl. No.:

9/404036

Inventors:

Peichun Peter Liu - Austin TX
Rajinder Paul Singh - Austin TX
Shih-Hsiung Steve Tung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1212

US Classification:

711110

Abstract:

A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

US Patent:

59059990, May 18, 1999

Filed:

Apr 29, 1996

Appl. No.:

8/638661

Inventors:

Peichun Peter Liu - Austin TX
Salim Ahmed Shah - Austin TX
Rajinder Paul Singh - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F12/08

US Classification:

711151

Abstract:

A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

US Patent:

57617147, Jun 2, 1998

Filed:

Apr 26, 1996

Appl. No.:

8/638263

Inventors:

Peichun Peter Liu - Austin TX
Rajinder Paul Singh - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711127

Abstract:

An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

US Patent:

60642459, May 16, 2000

Filed:

Feb 19, 1998

Appl. No.:

9/026087

Inventors:

Rajinder Paul Singh - Austin TX
Pei-Chun Liu - Austin TX
Song Kim - Santa Clara CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3027

US Classification:

327200

Abstract:

The present invention is directed to an apparatus for precharging complementary data circuits. The apparatus comprises two hold circuits, one for storing the data and the other for storing its complement. A signal for initiates precharging the hold circuits to the same signal level, where the signal for initiating the precharging of the hold circuits is dependent on the hold circuits' outputs.