Randy W Steele

US Patent:

53028651, Apr 12, 1994

Filed:

Feb 16, 1993

Appl. No.:

8/017851

Inventors:

Randy C. Steele - Folsom CA
Richard P. Vireday - Cameron Park CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19173
G06F 738

US Classification:

307465

Abstract:

A programmable gate array comprised of a number of configurable functional blocks. Each configurable functional block has a number (m) of inputs. A global interconnect matrix interconnects the configurable functional blocks. The global interconnect matrix provides for routing any combination of signals entering the matrix to any configurable functional block, up to and including the maximum number (m) of inputs of a configurable functional block. Each configurable functional block includes a product term array connected to the m inputs. The product term array can perform a logical AND of up to m bits. A compare term array is also connected to the m inputs. The compare term array can perform an identity compare of up to m/2 bits. A number n of macro cells are provided in each configurable functional block wherein the number n is less that the number m. An allocation circuit allocates the outputs of the compare term array and the product terms to a macro cell, any compare term being allocable in place of a product term to the macro cell.

US Patent:

54506085, Sep 12, 1995

Filed:

Aug 25, 1993

Appl. No.:

8/111663

Inventors:

Randy C. Steele - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

395800

Abstract:

A programmable logic device having the capability of initializing and resetting to a specified digital state. One or more clear/preset product terms are available for initializing and resetting the macrocells of the programmable logic device. Each macrocell can be either cleared to a "0" or preset to a "1" according to the clear/preset product terms. Control bits are used to select which of the clear/preset product terms, if any, are to be used to clear and/or preset a particular macrocell. These control bits are programmable for each of the macrocells, thereby allowing each macrocell to output either a "0" or a "1", as desired by the user, independent of the other macrocells. The macrocells can be cleared and preset asynchronously.

US Patent:

54711550, Nov 28, 1995

Filed:

Aug 19, 1994

Appl. No.:

8/293280

Inventors:

Randy C. Steele - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19177

US Classification:

326 39

Abstract:

A product term allocation arrangement in which each of a first plurality of input conductors may be programmably joined to a first plurality of output conductors and to a first plurality of AND gates, a second plurality of input conductors may be programmably joined to a second plurality of output conductors and to a second plurality of AND gates, apparatus which may be selected to perform either an AND or an OR function connected to receive input signals from one of the first plurality of AND gates and one of the second plurality of AND gates, and a plurality of OR gates connected to receive input signals from a selected number of the apparatus connected to receive input signals from one of the first plurality of AND gates and one of the second plurality of AND gates.

US Patent:

55748570, Nov 12, 1996

Filed:

Jan 31, 1994

Appl. No.:

8/189188

Inventors:

K. K. Ramakrishnan - Rancho Cordova CA
Randy Steele - Folsom CA
Joseph H. Salmon - Placerville CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1134

US Classification:

39518507

Abstract:

A circuit for testing the accuracy with which data is written from a first memory cell to a second memory cell including a shift register including master and slave portions, apparatus for placing data from the first memory cell into the master portion of the shift register and shifting the data into the slave portion of the shift register, apparatus for placing the data from the first memory cell into the second memory cell, apparatus for placing the data in the second memory cell back into the master portion of the shift register, and logic circuitry for testing the condition of the data in the master portion of the shift register against the condition of the data in the slave portion of the shift register to determine if the data has been correctly written into the second memory cell.

US Patent:

56357745, Jun 3, 1997

Filed:

Nov 24, 1993

Appl. No.:

8/157650

Inventors:

Randy C. Steele - Folsom CA

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H02J 100

US Classification:

307 86

Abstract:

A zero power circuit includes an upper power supply voltage pad, battery pad, a power control circuit, and a suppression circuit. The power control circuit provides power to the zero power circuit by switching between the battery pad and the upper power supply voltage pad. The suppression circuit is connected in series between the power control circuit and the battery pad. The suppression circuit includes a resistor connected in series between the battery pad and the power control circuit, wherein current flowing through the transistor during a latch condition causes the voltage to drop across the resistor, suppressing the latchup condition to the battery pad. The suppression circuit also includes a transistor connected in parallel with the resistor, the transistor having a gate, wherein a first signal applied to the gate turns off the transistor and a second signal applied to the gate turns on the transistor, wherein the resistor is shorted when the transistor is turned on.

US Patent:

58092811, Sep 15, 1998

Filed:

Jan 28, 1997

Appl. No.:

8/790271

Inventors:

Randy Charles Steele - Folsom CA
Duane H. Chinnow - Folsom CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1200

US Classification:

39549701

Abstract:

A field programmable gate array (FPGA) includes a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of "AND" gates and an array of "OR" gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

US Patent:

53090462, May 3, 1994

Filed:

Sep 30, 1992

Appl. No.:

7/954308

Inventors:

Randy C. Steele - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19173

US Classification:

307465

Abstract:

In a programmable logic device having a plurality of gates capable of being programmed according to a plurality of product terms representing logic functions, an apparatus for allocating the product terms to a plurality of outputs. A first set of product terms are steerable to one of at least two outputs. A second set of product terms is permanently assigned to a predetermined output. The second set is comprised of more product terms than the first set, wherein the average number of product terms per output is low, yet a user has the flexibility of implementing logic functions requiring a relatively large number of product terms.

US Patent:

56758243, Oct 7, 1997

Filed:

Dec 15, 1995

Appl. No.:

8/573584

Inventors:

Randy C. Steele - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1130

US Classification:

395800

Abstract:

A programmable logic device having a plurality of gates which can be programmed to implement a plurality of product terms for representing logic functions, wherein an input signal is processed according to the logic functions, and a resulting output signal is generated having a selectable output voltage level. A desired output voltage level is specified. A generator supplies the desired output voltage to an output buffer of the programmable logic device. This generator may operate independently from the generator used to supply power to the programmable logic device. The processed signal drives the output buffer, and the output signal from the output buffer corresponds to the desired output voltage.