Raymond J Eberhard

US Patent:

6442655, Aug 27, 2002

Filed:

Oct 30, 2000

Appl. No.:

09/699957

Inventors:

Raymond J. Eberhard - Endicott NY
Eddie Wong - Apalachin NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711151, 711150, 710 3, 710 52

Abstract:

A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.

US Patent:

6457144, Sep 24, 2002

Filed:

Dec 8, 1998

Appl. No.:

09/206326

Inventors:

Raymond J. Eberhard - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 305

US Classification:

714 45, 710 32, 710 57, 712227

Abstract:

A memory controller used to manage the memory interface (main store interface) for processor and input and output (I/O) device access, includes a trace array used for accumulating trace data signals to be stored to main store, control logic used to determine when the array should be updated and when its contents should be stored to main store, an address register which provides the starting address of main store assigned to store trace data, an offset address register which identifies the current address to store trace data, and a space size register used to identify the amount of main store reserved to store trace data. In a first implementation, the contents of the trace array are moved to main store when the trace array becomes full. An alternative implementation provides additional control registers and logic which allow memory to be updated from the trace array when the memory interface is not busy.

US Patent:

6922788, Jul 26, 2005

Filed:

Sep 19, 2001

Appl. No.:

09/955821

Inventors:

Raymond J. Eberhard - Endicott NY, US
James William Feeney - Endicott NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F001/32

US Classification:

713320, 713324

Abstract:

A method for conserving energy in a computing unit and transferring data between the computing unit and an external source. The computing unit is in a power saving mode. The method includes receiving at the computing unit a request from an external source, determining which components of the computing unit are required to respond to the request, selectively activating, from the power saving mode, the components of the computing unit necessary to respond the request, and responding to the request using the selectively activated components of the computing unit. As one example, the computing unit may comprise a laptop, and the external source may comprise a PDA, and the request may include a request from the PDA to retrieve data from or store data on the laptop.

US Patent:

7561059, Jul 14, 2009

Filed:

Nov 9, 2006

Appl. No.:

11/558137

Inventors:

Vincent V. Diluoffo - Sandy Hook CT, US
Raymond J. Eberhard - Endwell NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G08B 21/00

US Classification:

340638, 340509, 340590, 340635, 34063613, 34063617, 340652, 361104, 327525, 327526

Abstract:

A circuit that employs an anti-tamper sensor includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element. The decoy coupling element will cause the circuit element not to operate normally if the decoy coupling element has a selected physical property of the selective coupling element in the first state.

US Patent:

7755502, Jul 13, 2010

Filed:

Oct 10, 2007

Appl. No.:

11/869807

Inventors:

Vincent V Diluoffo - Sandy Hook CT, US
Raymond J Eberhard - Endwell NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G08B 21/00

US Classification:

340638, 340509, 340590, 340635, 34063613, 34063617, 340652, 361104, 327525, 327526

Abstract:

A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element. The decoy coupling element will cause the circuit element not to operate normally if the decoy coupling element has a selected physical property of the selective coupling element in the first state.

US Patent:

20060139295, Jun 29, 2006

Filed:

Dec 23, 2004

Appl. No.:

11/021503

Inventors:

Raymond Eberhard - Endwell NY, US
Mark Hodges - Owego NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 3/36

US Classification:

345101000

Abstract:

A cholesteric display includes a display controller and a database. The database includes a control program for programming the operation of the display controller, a display field for storing information to be displayed at the cholesteric display, and a temperature range field for storing the temperature range of the environment of the cholesteric display. An input device is provided for loading control program, display information, and temperature or temperature range data to the database.

US Patent:

60981156, Aug 1, 2000

Filed:

Apr 8, 1998

Appl. No.:

9/057409

Inventors:

Raymond J. Eberhard - Endicott NY
John M. Kaiser - late of Cedar Park TX
Warren E. Maule - Cedar Park TX
Eddie Wong - Apalachin NY
Vincent P. Zeyak - Apalachin NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710 7

Abstract:

System and method reading data from storage by speculatively accessing storage and overlapping data bus access with status determination, thereby reducing storage read access latency. Also, a system and method is provided for reducing storage read access latency by accessing a data bus substantially simultaneously with availability of data from storage. Upon receipt of a storage read request, and before status determination, the requested data is read from storage. Optionally, depending upon bus architecture or the need to minimize control circuitry, control of the data bus may speculatively be sought so that data may be loaded to the data bus upon availability from main storage, still whether or not status has been resolved. Subsequently, if status cancels the read request, further data bus loading is terminated.

US Patent:

53865316, Jan 31, 1995

Filed:

May 15, 1991

Appl. No.:

7/700732

Inventors:

Bartholomew Blaner - Newark Valley NY
Raymond J. Eberhard - Endicott NY
Thomas L. Jeremiah - Endwell NY
Michael J. Mack - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1204
G06F 1206

US Classification:

395425

Abstract:

An instruction processing unit (IPU) and a storage array, a storage-to-instruction-processing-unit interface, including a hardware accelerator for cross-boundary storage access with a cross-boundary buffer for providing residual read and write data in support of high speed block concurrent accessing of multi-word operands of a computer system. A cross-boundary buffer (CBB) is used, coupled to a write rotating shifter, a write merger (WMERGE) and a write merge controller (WMCTL) which is coupled for an input to said control register (CREG) for sequencing data transmitted on the data bus for merger with data contained in the cross-boundary buffer (CBB) by the write merger before it is latched in a data bus out register, and for simultaneously also latching the data in the cross-boundary buffer (CBB), and for writing data from the data bus out register into the storage array in the next clock cycle of the instruction processor at the doubleword address addressed. The cross-boundary buffer (CCB) is also coupled to a read rotating shifter (RROTATE), a read merger (RMERGE) and a read merge controller which responds to control instruction sequencing. The storage-to-instruction-processing-unit interface operates on multiple words, with residues from a second and subsequent accesses allowing continuation of the accessing process beyond two memory words.