Richard E Demers

US Patent:

6771643, Aug 3, 2004

Filed:

Apr 28, 2000

Appl. No.:

09/561121

Inventors:

Richard Lucien Demers - Glendale AZ
Jeffrey David Scott - Glendale AZ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04Q 1100

US Classification:

370387, 370230, 370365, 370445

Abstract:

A multi-packet-switch system having a standard primary switch interconnect to handle inter-switch packet traffic, separate buffer areas for each primary interconnect and the device ports, the ability to identify specific packet streams by an identifier in each packet, and the ability to specifically manage static routing of packets based on the packet stream identifier. Creating secondary switch interconnects between device ports, and routing identified packet streams to these secondary switch interconnects. The secondary switch interconnects can be dedicated to identified packet streams, thus eliminating primary interconnect buffer contention with other packet streams.

US Patent:

55070000, Apr 9, 1996

Filed:

Sep 26, 1994

Appl. No.:

8/311797

Inventors:

Wilbur L. Stewart - Phoenix AZ
Ronald E. Lange - Glendale AZ
Richard L. Demers - Peoria AZ
Jeffrey D. Weintraub - Scottsdale AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 900
G06F 9302

US Classification:

395800

Abstract:

In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.

US Patent:

58945814, Apr 13, 1999

Filed:

Apr 15, 1993

Appl. No.:

8/048339

Inventors:

Wilbur L. Stewart - Phoenix AZ
Richard L. Demers - Peoria AZ
Ronald E. Lange - Glendale AZ
Lowell D. McCulley - Glendale AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 700

US Classification:

39580001

Abstract:

In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or "don't care". If a field is marked as "don't care", the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word. If the guarded fields in the first virtual control word align with the "don't care" fields in the second virtual control word and vice versa, the two virtual control words can be combined into a single control word containing the contents of the guarded fields from both virtual control words, the remaining fields, if any, remaining "don't care". This process may be reiterated to determine if the combined control word can be further combined with another virtual control word.

US Patent:

55686222, Oct 22, 1996

Filed:

Apr 15, 1993

Appl. No.:

8/048323

Inventors:

Wilbur Stewart - Phoenix AZ
Richard L. Demers - Peoria AZ
Ronald E. Lange - Glendale AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 922

US Classification:

395375

Abstract:

Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A set of control fields are required to control the active elements of the unit to cause the unit to execute a large number of different basic operations. Typically the required set of control fields are included in control words stored in a control store controlling the unit during the execution of a basic operation. Obtaining some of the set of required control fields from other sources available within the unit results in a significant reduction in the number of control words stored in the control store without reducing the functionality of the unit.

US Patent:

56447612, Jul 1, 1997

Filed:

Jun 5, 1992

Appl. No.:

7/893871

Inventors:

Ronald W. Yoder - Mesa AZ
Ronald E. Lange - Glendale AZ
William A. Shelly - Phoenix AZ
Russell W. Guenthner - Glendale AZ
Richard L. Demers - Peoria AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 922

US Classification:

395595

Abstract:

In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

US Patent:

57375453, Apr 7, 1998

Filed:

May 21, 1996

Appl. No.:

8/651698

Inventors:

Philip Wszolek - Phoenix AZ
Barry Martin Davis - Phoenix AZ
Brian Neil Fall - Chandler AZ
Richard Demers - Peoria AZ

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01J 1300

US Classification:

395288

Abstract:

A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.