Rick A Leininger

US Patent:

6489007, Dec 3, 2002

Filed:

Dec 14, 2000

Appl. No.:

09/736794

Inventors:

Ford B. Grigg - Meridian ID
James M. Ocker - Kuna ID
Rick A. Leininger - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B 310

US Classification:

428132, 428131, 428134, 428135, 428136, 283 37, 283 70, 257798

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographicaily formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed. A machine vision system may be used in such methods so as to recognize the position and orientation of a semiconductor device or other substrate to be stereolithographically marked.

US Patent:

6585927, Jul 1, 2003

Filed:

Dec 14, 2000

Appl. No.:

09/736624

Inventors:

Ford B. Grigg - Meridian ID
James M. Ocker - Kuna ID
Rick A. Leininger - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B29C 3508

US Classification:

264401, 264132, 264236, 26427217, 264340

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed. A machine vision system may be used in such methods so as to recognize the position and orientation of a semiconductor device or other substrate to be stereolithographically marked.

US Patent:

6635333, Oct 21, 2003

Filed:

Aug 29, 2001

Appl. No.:

09/942242

Inventors:

Ford B. Grigg - Meridian ID
James M. Ocker - Kuna ID
Rick A. Leininger - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B 310

US Classification:

428134, 428132, 428135, 428136, 283 37, 283 74, 283 81, 257797

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When the marking is formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package structure. The marking may be formed as apertures through or recessed areas in one or more stereolithographically fabricated layers of material. Alternatively, the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. The marking may be formed directly on a surface of a packaged or bare semiconductor device component. As an alternative, the marking can be fabricated separately from a semiconductor device component, then secured thereto. Methods of stereolithographically marking semiconductor device components are also disclosed.

US Patent:

6703105, Mar 9, 2004

Filed:

Nov 21, 2002

Appl. No.:

10/301209

Inventors:

Ford B. Grigg - Meridian ID
James M. Ocker - Kuna ID
Rick A. Leininger - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B 310

US Classification:

428132, 428134, 428135, 428136, 283 70, 257798

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed. A machine vision system may be used in such methods so as to recognize the position and orientation of a semiconductor device or other substrate to be stereolithographically marked.

US Patent:

6706374, Mar 16, 2004

Filed:

Nov 21, 2002

Appl. No.:

10/301087

Inventors:

Ford B. Grigg - Meridian ID
James M. Ocker - Kuna ID
Rick A. Leininger - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B 310

US Classification:

428199, 4281951, 428132, 257506

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed. A machine vision system may be used in such methods so as to recognize the position and orientation of a semiconductor device or other substrate to be stereolithographically marked.

US Patent:

6939501, Sep 6, 2005

Filed:

Jun 26, 2003

Appl. No.:

10/608749

Inventors:

Ford B. Grigg - Meridian ID, US
James M. Ocker - Kuna ID, US
Rick A. Leininger - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B29C035/08
B29C041/02
B29C070/88
B29C071/02

US Classification:

264401, 264132, 264236, 26427217, 264340

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed. A machine vision system may be used in such methods so as to recognize the position and orientation of a semiconductor device or other substrate to be stereolithographically marked.

US Patent:

20050285278, Dec 29, 2005

Filed:

Aug 31, 2005

Appl. No.:

11/216895

Inventors:

Ford Grigg - Meridian ID, US
James Ocker - Kuna ID, US
Rick Leininger - Meridian ID, US

International Classification:

H01L023/48

US Classification:

257781000

Abstract:

A marking for a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The marking is configured to contrast visually with a semiconductor device component, and may include features that are configured to protrude from the semiconductor device component recessed features to provide desired indicia. Materials that contrast visually with one another may also be used to form the marking.

US Patent:

6337122, Jan 8, 2002

Filed:

Jan 11, 2000

Appl. No.:

09/481779

Inventors:

Ford B. Grigg - Meridian ID
James M. Ocker - Kuna ID
Rick A. Leininger - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B32B 300

US Classification:

428195, 428199, 257506

Abstract:

A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When the marking is formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package structure. The marking may be formed as apertures through or recessed areas in one or more stereolithographically fabricated layers of material. Alternatively, the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. The marking may be formed directly on a surface of a packaged or bare semiconductor device component. As an alternative, the marking can be fabricated separately from a semiconductor device component, then secured thereto. Methods of stereolithographically marking semiconductor device components are also disclosed.