Robert A Bateman

US Patent:

6643200, Nov 4, 2003

Filed:

Apr 5, 2000

Appl. No.:

09/543131

Inventors:

Lawrence T. Clark - Phoenix AZ
Robert D. Bateman - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

365205, 365207, 365226

Abstract:

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a sense amp connected to a plurality of bit lines with bit line transistors. Each of the bit line transistors may be connected to a sense amp enable transistor so that together, the coupling and sense amp enable transistors connect the sense amp to a power supply voltage.

US Patent:

6831868, Dec 14, 2004

Filed:

Dec 5, 2002

Appl. No.:

10/310287

Inventors:

Robert D. Bateman - Scottsdale AZ
James R. Harness - Chandler AZ
Kayla L. Chalmers - Austin TX

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

365200, 365201

Abstract:

A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.

US Patent:

6862663, Mar 1, 2005

Filed:

Jun 30, 2000

Appl. No.:

09/609567

Inventors:

Robert D. Bateman - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711133, 711100, 711118, 711136, 711154

Abstract:

Briefly, in accordance with one embodiment of the invention, a method by which one or more ways of a cache may be locked so that they are not overwritten with data. Further, the ways of a cache that are locked may be given higher priority than the most recently used or accessed ways.

US Patent:

6985392, Jan 10, 2006

Filed:

Sep 1, 2004

Appl. No.:

10/931698

Inventors:

Robert D. Bateman - Scottsdale AZ, US
James R. Harness - Chandler AZ, US
Kayla L. Chalmers - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365200, 365201

Abstract:

A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.