Ronald A Piro from 6 Peacham Ln, Essex Junction, VT 05452, age 65, Phone: 8028781135

Us Patents

Compilable Writeable Read Only Memory (Rom) Built With Register Arrays
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US Patent:

6600673, Jul 29, 2003
Filed:

Jan 31, 2003
Appl. No.:

10/248599
Inventors:

Peter F. Croce - Essex Junction VT
Steven M. Eustis - Essex Junction VT
Ronald A. Piro - Essex Junction VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G11C 1712
US Classification:

365104, 365103, 365 94, 36518905
Abstract:

A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.

Embedded Photon Emission Calibration (Epec)
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US Patent:

20130211749, Aug 15, 2013
Filed:

Feb 15, 2012
Appl. No.:

13/396775
Inventors:

Albert M. Chu - Essex VT, US
Ronald A. Piro - Essex Junction VT, US
Daryl M. Seitzer - Essex Junction VT, US
Rohit Shetty - Essex Junction VT, US
Thomas W. Wyckoff - Jeffersonville VT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G01R 31/308
G06F 19/00
US Classification:

702 58
Abstract:

A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.

Read Only Memory (Rom) With Redundancy
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US Patent:

20130275821, Oct 17, 2013
Filed:

Apr 12, 2012
Appl. No.:

13/445187
Inventors:

George M. BRACERAS - Essex Junction VT, US
Albert M. CHU - Essex VT, US
Kevin W. Gorman - Fairfax VT, US
Michael R. OUELLETTE - Westford VT, US
Ronald A. PIRO - Essex Junction VT, US
Daryl M. SEITZER - Essex Junction VT, US
Rohit SHETTY - Essex Junction VT, US
Thomas W. WYCKOFF - Jeffersonville VT, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

G11C 29/12
G06F 11/27
G11C 29/00
US Classification:

714718, 365200, 714E11169
Abstract:

A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

Method Of Combining Gate Array And Standard Cell Circuits On A Common Semiconductor Chip
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US Patent:

47866136, Nov 22, 1988
Filed:

Feb 24, 1987
Appl. No.:

7/018239
Inventors:

Elliot L. Gould - Colchester VT
Douglas W. Kemerer - Essex Junction VT
Lance A. McAllister - Williston VT
Ronald A. Piro - South Burlington VT
Guy R. Richardson - Milton VT
Deborah A. Wellburn - Colchester VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2138
US Classification:

437 48
Abstract:

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum ground rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguosuly arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing the chips density and performance versus hardware turn-around-time.

Low-Power, Tristate, Off-Chip Driver Circuit
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US Patent:

56296347, May 13, 1997
Filed:

Aug 21, 1995
Appl. No.:

8/517227
Inventors:

Allen R. Carl - Essex Junction VT
Ronald A. Piro - Williston VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H03K 190185
US Classification:

326 27
Abstract:

An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. Compensator circuits, one for the N-channel pull-down, and one for the P-channel pull-up, are used to prevent the transition from high-to-low or low-to-high from being too rapid, which could cause noise due to inductance of the package leads. A feedback circuit halts the operation of the compensator circuits after a short interval. An overvoltage circuit formed in a well of the semiconductor chip holding the driver circuit, having an input coupled to receive the data output of the predriver circuit going to the P-channel pull-up, also functions to prevent damage to the output driver circuit due to overvoltage on the output node. A stack of diodes connected in a forward direction between the N-well of the P-channel pull-up transistor and the positive terminal of the voltage supply serves to clamp the output node if it tends to go above a selected overvoltge level.

Method Of Combining Gate Array And Standard Cell Circuits On A Common Semiconductor Chip
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US Patent:

53695950, Nov 29, 1994
Filed:

Mar 28, 1991
Appl. No.:

7/676655
Inventors:

Elliot L. Gould - Colchester VT
Douglas W. Kemerer - Essex Junction VT
Lance A. McAllister - Williston VT
Ronald A. Piro - South Burlington VT
Guy R. Richardson - Milton VT
Deborah A. Wellburn - Colchester VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H03K 19177
US Classification:

364490
Abstract:

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Method Of Combining Gate Array And Standard Cell Circuits On A Common Semiconductor Chip
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US Patent:

50519174, Sep 24, 1991
Filed:

Mar 18, 1988
Appl. No.:

7/169908
Inventors:

Elliot L. Gould - Colchester VT
Douglas W. Kemerer - Essex Junction VT
Lance A. McAllister - Williston VT
Ronald A. Piro - South Burlington VT
Guy R. Richardson - Milton VT
Deborah A. Wellburn - Colchester VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2170
G06F 1560
US Classification:

364489
Abstract:

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Cmos Off Chip Driver Circuit
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US Patent:

51516195, Sep 29, 1992
Filed:

Oct 11, 1990
Appl. No.:

7/595911
Inventors:

John S. Austin - Essex Junction VT
Ronald A. Piro - South Burlington VT
Douglas W. Stout - Milton VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H03K 19017
H03K 19096
H03K 17687
H03K 1704
US Classification:

307473
Abstract:

A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor. A first input terminal is coupled to the gate electrode of the pull up transistor through a transmission gate including a first N-channel field effect transistor arranged in parallel with a second P-channel field effect transistor, with a gate electrode of the first N-channel transistor being connected to the first voltage source and the gate electrode of the second P-channel transistor being connected to the output terminal.