Sam S Liu

US Patent:

8392745, Mar 5, 2013

Filed:

Apr 26, 2010

Appl. No.:

12/767226

Inventors:

Greg Goodemote - Tustin CA, US
Khan Kibria - Mission Viejo CA, US
Mark N. Fullerton - Austin TX, US
Niray P. Dagli - Placentia CA, US
Liang Deng - Sunnyvale CA, US
Sam Liu - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 1/00

US Classification:

713501, 713300, 713320, 713322

Abstract:

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.

US Patent:

20070280396, Dec 6, 2007

Filed:

May 31, 2007

Appl. No.:

11/806397

Inventors:

Sam H. Liu - Irvine CA, US
Zhiqing Zhuang - Irvine CA, US
Chaoyang Zhao - Irvine CA, US
Vinay Bhasin - Irvine CA, US
Chenmin Zhang - Irvine CA, US
Lawrence J. Madar - San Francisco CA, US
Vafa J. Rakshani - Newport Coast CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00

US Classification:

375372

Abstract:

Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

US Patent:

62593145, Jul 10, 2001

Filed:

Feb 12, 1999

Appl. No.:

9/249908

Inventors:

Sam H. Liu - Los Angeles CA
Edward L. Niu - Redondo Beach CA
Vincent C. Moretti - Torrance CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

H04B 1700

US Classification:

329304

Abstract:

The invention is a demodulator (50, 100) and a method of data reception and testing of a demodulator. A demodulator in accordance with the invention includes an input signal source (52, 102) having an output which during data reception is a data signal and which during testing of the demodulator is a reference signal; a tuner (54, 101) having a tuner input coupled to the output of the input signal source and a tuner output, the tuner including a frequency converter (20, 36) which frequency shifts the data signal to a lower carrier frequency during data reception to cause the tuner to output at the tuner output the lower carrier frequency modulated with the data signal and which upwardly frequency shifts the reference signal to a test carrier frequency during the testing; and a test data source (56, 105) which applies a test data signal to the tuner during the testing to cause the tuner to output at the tuner output the test carrier frequency modulated with the test data signal.

US Patent:

62631950, Jul 17, 2001

Filed:

Feb 12, 1999

Appl. No.:

9/249904

Inventors:

Edward L. Niu - Redondo Beach CA
Sam H. Liu - Los Angeles CA
Gregory S. Caso - Hermosa Beach CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

H03K 900

US Classification:

4551501

Abstract:

A wideband digital tuner (14') has an analog front-end section (10), a high speed analog-to-digital converter (12), demultiplexer (13) and a plurality of filters (34. sub. 1 -34. sub. 2) arranged in a parallel input architecture to process wideband digital data received at extremely high sampling rates, such as at 2 Gsps (giga-samples per second). The tuner greatly attenuates an undesired spectral half of the wide bandwidth digital spectrum of the incoming digital signal using a complex band-pass filter, such as a Hilbert Transform filter. The tuner places the remaining half of the wide bandwidth digital spectrum of the incoming digital signal at complex baseband and down samples by 2. The architecture of the tuner can be partitioned into two separate halves which are hardware copies of each other.