Samuel X Liu

US Patent:

7339592, Mar 4, 2008

Filed:

Jul 13, 2004

Appl. No.:

10/889730

Inventors:

John Erik Lindholm - Saratoga CA, US
Ming Y. Siu - Sunnyvale CA, US
Simon S. Moy - Los Altos CA, US
Samuel Liu - Cupertino CA, US
John R. Nickolls - Los Altos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/02
G06F 13/00
G09G 5/36

US Classification:

345543, 345559, 345536

Abstract:

An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.

US Patent:

7444081, Oct 28, 2008

Filed:

Sep 17, 2004

Appl. No.:

10/944327

Inventors:

Samuel Xing Liu - San Jose CA, US
Yu Sheng Bai - Los Altos Hills CA, US

Assignee:

Futurewei Technologies, Inc. - Plano TX

International Classification:

H04B 10/00

US Classification:

398138, 398183, 398201

Abstract:

A method and system is disclosed to optically transport data at a data rate of about 5 Gbps without chromatic dispersion compensation. After receiving a first data stream at a data rate of about 2. 5 Gbps and a second data stream at a data rate of about 2. 5 Gbps, the first and second data streams are combined into a third data stream at a data rate of about 5 Gbps by interleaving the first data stream and the second data stream, wherein the third data stream is modulated for optically transporting the same from a transmission end.

US Patent:

7680988, Mar 16, 2010

Filed:

Oct 30, 2006

Appl. No.:

11/554563

Inventors:

John R. Nickolls - Los Altos CA, US
Brett W. Coon - San Jose CA, US
Ming Y. Siu - Santa Clara CA, US
Stuart F. Oberman - Sunnyvale CA, US
Samuel Liu - Cupertino CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 13/16

US Classification:

711149, 711130, 711131

Abstract:

A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e. g. , from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.

US Patent:

7760972, Jul 20, 2010

Filed:

Mar 27, 2006

Appl. No.:

11/389812

Inventors:

Joe Wen - Fremont CA, US
Samuel Liu - San Jose CA, US
Giovanni Barbarossa - Saratoga CA, US

Assignee:

Oclaro Technology, plc - Paignton

International Classification:

G02B 6/26
G02B 6/42

US Classification:

385 22, 385 16, 385 18, 385 23, 385 24, 385 39, 385 47, 385140

Abstract:

The present invention provides a switch assembly for use with a single-port OPM to realize a multi-port OPM having improved reliability. In one embodiment, an N×1 optical switch assembly, wherein N is an integer greater than one, is provided. The optical switch assembly includes N optical input ports, N micro-electro-mechanical system (MEMS) variable optical attenuators (VOAs), where each MEMS VOA is optically coupled to a respective optical input port and is operable between an on position and an off position, and an N×1 optical combiner optically coupled to the N MEMS VOAs. Each MEMS VOA is configured to transmit an optical signal from a respective one of the optical input ports to the N×1 optical combiner in the on position and to not transmit the optical signal in the off position.

US Patent:

7834881, Nov 16, 2010

Filed:

Nov 1, 2006

Appl. No.:

11/555649

Inventors:

Samuel Liu - Cupertino CA, US
John Erik Lindholm - Saratoga CA, US
Ming Y Siu - Santa Clara CA, US
Brett W. Coon - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/36
G09G 5/39
G06F 15/80

US Classification:

345557, 345531, 345505

Abstract:

An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.

US Patent:

7885546, Feb 8, 2011

Filed:

Oct 23, 2007

Appl. No.:

11/877621

Inventors:

Samuel Liu - San Jose CA, US
Xiaodong Duan - Fremont CA, US
Giovanni Barbarossa - Saratoga CA, US

Assignee:

Oclaro (North America), Inc. - San Jose CA

International Classification:

H04J 14/08

US Classification:

398 98

Abstract:

A method and apparatus for multiplexing multiple Ethernet-based data streams in an optical network reduce the number of optical transceivers required by the optical network. Multiple data streams are multiplexed into a combined data stream, transmitted from a node in the optical network as the combined data stream, and demultiplexed at the receiving node. Data streams are multiplexed and demultiplexed at the bit level, and packets from each data stream are routed based on a VLAN tag that is contained in the header of each packet. By transmitting the information contained in multiple data streams as a single multiplexed data stream, the number of optical transceivers required for the optical network may be reduced by more than half. An optical supervisory channel may also be bundled with one of the data streams to eliminate the need for a dedicated transceiver for the optical supervisory channel.

US Patent:

8578387, Nov 5, 2013

Filed:

Jul 31, 2007

Appl. No.:

11/831873

Inventors:

Peter C. Mills - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
John Erik Lindholm - Saratoga CA, US
Samuel Liu - Cupertino CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718105, 712 20, 712 22, 712200, 712208

Abstract:

An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by a first type of processing engine and a third type of program instructions can only be executed by a second type of processing engine. A second type of program instructions can be executed by the first and the second type of processing engines. An assignment unit may be configured to dynamically determine which of the two processing engines executes any program instructions of the second type in order to balance the workload between the heterogeneous processing engines.

US Patent:

20090116847, May 7, 2009

Filed:

Nov 5, 2007

Appl. No.:

11/935324

Inventors:

Xiaodong DUAN - Fremont CA, US
Samuel Liu - San Jose CA, US
Giovanni Barbarossa - Saratoga CA, US

International Classification:

H04B 10/00

US Classification:

398137

Abstract:

A supervisory signal is superimposed onto a high-speed data stream so that the number of optical transceivers needed by an optical network is reduced. The supervisory signal is superimposed onto the high-speed data stream as an in-band modulation of the data stream. To improve signal-to-noise ratio of the in-band supervisory signal, the supervisory signal is first modulated to a higher frequency before it is superimposed onto the high-speed data stream.