Sarah A Niroumand

US Patent:

20110193226, Aug 11, 2011

Filed:

Feb 8, 2010

Appl. No.:

12/701800

Inventors:

Kyle K. Kirby - Eagle ID, US
Kunal R. Parekh - Boise ID, US
Sarah A. Niroumand - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 23/48
H01L 21/768
H01L 23/488

US Classification:

257738, 257774, 438667, 438613, 257E21585, 257E23011, 257E23023

Abstract:

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

US Patent:

20120267786, Oct 25, 2012

Filed:

Apr 22, 2011

Appl. No.:

13/092434

Inventors:

Kyle K. Kirby - Eagle ID, US
Kunal R. Parekh - Boise ID, US
Philip J. Ireland - Nampa ID, US
Sarah A. Niroumand - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 23/48
H01L 21/60

US Classification:

257770, 438637, 438667, 257E21507, 257E23011

Abstract:

Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

US Patent:

20110042821, Feb 24, 2011

Filed:

Aug 21, 2009

Appl. No.:

12/545196

Inventors:

Kyle K. Kirby - Eagle ID, US
Sarah A. Niroumand - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23/48
H01L 21/768

US Classification:

257774, 438637, 438666, 257E23011, 257E21577, 257E21575

Abstract:

Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.

US Patent:

20220336273, Oct 20, 2022

Filed:

Jun 27, 2022

Appl. No.:

17/850848

Inventors:

- Boise ID, US
Kunal R. Parekh - Boise ID, US
Sarah A. Niroumand - Boise ID, US

International Classification:

H01L 21/768
H01L 23/48
H01L 23/00
H01L 25/065
H01L 25/00
H01L 21/306
H01L 21/311

Abstract:

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

US Patent:

20200312714, Oct 1, 2020

Filed:

Jun 15, 2020

Appl. No.:

16/902115

Inventors:

- Boise ID, US
Kunal R. Parekh - Boise ID, US
Sarah A. Niroumand - Boise ID, US

International Classification:

H01L 21/768
H01L 23/48
H01L 23/00
H01L 25/065
H01L 25/00
H01L 21/306
H01L 21/311

Abstract:

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

US Patent:

20200294854, Sep 17, 2020

Filed:

Mar 23, 2020

Appl. No.:

16/826651

Inventors:

- Boise ID, US
Sarah A. Niroumand - Boise ID, US

International Classification:

H01L 21/768
H01L 23/48

Abstract:

Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.

US Patent:

20170372961, Dec 28, 2017

Filed:

Aug 28, 2017

Appl. No.:

15/687636

Inventors:

- Boise ID, US
Sarah A. Niroumand - Boise ID, US

International Classification:

H01L 21/768
H01L 23/48
H01L 23/00

Abstract:

Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.

US Patent:

20160233160, Aug 11, 2016

Filed:

Apr 19, 2016

Appl. No.:

15/133121

Inventors:

- Boise ID, US
Kunal R. Parekh - Boise ID, US
Philip J. Ireland - Nampa ID, US
Sarah A. Niroumand - Boise ID, US

International Classification:

H01L 23/522
H01L 23/532
H01L 23/528
H01L 21/768

Abstract:

Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.