Scott S Hunter

US Patent:

20190379376, Dec 12, 2019

Filed:

Aug 26, 2019

Appl. No.:

16/551516

Inventors:

- Kansas City MO, US
Cooper Tracy - Kansas City MO, US
Scott Hunter - Kansas City MO, US

International Classification:

H03K 17/785
H03K 17/687
H02J 4/00
H02M 7/217
H02M 1/32

Abstract:

A method for high speed switching comprises receiving voltage inputs at a bridge rectifier, receiving a logic input signal at an optical isolator and generating an output signal from the optical isolator based on the logic input signal, and driving a gate of a field effect transistor (FET) via the output signal of the optical isolator, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The method further includes limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.

US Patent:

20180316347, Nov 1, 2018

Filed:

Jul 2, 2018

Appl. No.:

16/025984

Inventors:

- Kansas City MO, US
Cooper Tracy - Kansas City MO, US
Scott Hunter - Kansas City MO, US

International Classification:

H03K 17/785
H03K 17/687
H02M 1/32

Abstract:

A switching circuit includes a bridge rectifier to receive voltage inputs and an optical isolator to receive a logic input signal and generate an output signal based on the logic input signal. The high speed switching circuit also includes a field effect transistor (FET) with a source connected to a negative output of the bridge rectifier, a drain connected to a positive output of the bridge rectifier through a load, and a gate driven by the output signal of the optical isolator. First and second resistors connect the voltage inputs to the gate of the FET through first and second diodes. The first and second resistors and the first and second diodes limit current flowing to the gate of the FET. A Zener diode connected to the gate of the FET limits voltage to the gate of the FET below a maximum voltage rating of the FET.

US Patent:

20160344385, Nov 24, 2016

Filed:

Aug 4, 2016

Appl. No.:

15/228780

Inventors:

- Kansas City MO, US
Cooper Tracy - Kansas City MO, US
Scott Hunter - Kansas City MO, US

International Classification:

H03K 17/785
H03K 17/687
H02J 4/00

Abstract:

A switching circuit includes a bridge rectifier to receive voltage inputs across a load and an optical isolator to receive a logic input signal and generate an output signal based on the logic input signal. The high speed switching circuit also includes a field effect transistor (FET) with a source connected to a negative output of the bridge rectifier, a drain connected to a positive output of the bridge rectifier through a second load, and a gate driven by the output signal of the optical isolator. First and second resistors connect the voltage inputs to the gate of the FET through first and second diodes. The first and second resistors and the first and second diodes limit current flowing to the gate of the FET. A Zener diode connected to the gate of the FET limits voltage to the gate of the FET below a maximum voltage rating of the FET.