Scott A Johannesmeyer

Address:

1903 Drew Ln, Richardson, TX 75082

Phone:

9726693724

VIN:

JTEDS43A292087839

Make:

TOYOTA

Model:

HIGHLANDER

Year:

2009

US Patent:

6709974, Mar 23, 2004

Filed:

Dec 19, 2002

Appl. No.:

10/322763

Inventors:

David Permana - Dallas TX
Albert Cheng - Richardson TX
Jeff A. West - Dallas TX
Brock W. Fairchild - Allen TX
Scott A. Johannesmeyer - Richardson TX
Chris M. Bowles - Plano TX
Thomas D. Bonifield - Dallas TX
Rajesh Tiwari - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438633, 438637, 438687

Abstract:

A method of preventing seam defects on narrow, isolated lines of 0. 3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0. 6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

US Patent:

20020023254, Feb 21, 2002

Filed:

Aug 17, 2001

Appl. No.:

09/932310

Inventors:

Hongmei Liao - Tewksbury MA, US
Scott Johannesmeyer - Richardson TX, US

International Classification:

G06F017/50

US Classification:

716/008000

Abstract:

A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.

US Patent:

20210398910, Dec 23, 2021

Filed:

Jul 15, 2021

Appl. No.:

17/376876

Inventors:

- Dallas TX, US
William Keith McDONALD - Kemp TX, US
Scott Alexander JOHANNESMEYER - Richardson TX, US
Robert Paul LUCKIN - Plano TX, US
Stephen Arlon MEISNER - Allen TX, US

International Classification:

H01L 23/544
G03F 7/20
H01L 21/027

Abstract:

An integrated circuit includes a circuit area, and first and second scribe line portions. The first scribe line portion borders a first side of the circuit area, and the second scribe line portion borders a different second side of the circuit area. A plurality of dummy metal structures are located in the first and second scribe line portions, each of the dummy metal structures being located about at a lattice point of a same two-dimensional grid.

US Patent:

20210104468, Apr 8, 2021

Filed:

Nov 11, 2019

Appl. No.:

16/679997

Inventors:

- Dallas TX, US
William Keith McDONALD - Kemp TX, US
Scott Alexander JOHANNESMEYER - Richardson TX, US
Robert Paul LUCKIN - Plano TX, US
Stephen Arlon MEISNER - Allen TX, US

International Classification:

H01L 23/544
H01L 21/027
G03F 7/20

Abstract:

In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.