Scott W Mitchell

US Patent:

6438429, Aug 20, 2002

Filed:

Dec 3, 1999

Appl. No.:

09/454796

Inventors:

Tan Thanh Ho - Santa Clara CA
Scott William Mitchell - San Jose CA
Andrew Nakao - Fremont CA
Ngo Thanh Ho - San Jose CA
George Kwan - Sunnyvale CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 126

US Classification:

700 22, 713340

Abstract:

A circuit and method thereof for indicating availability of a power source other than a first power source in a computer system peripheral device (such as a network adapter) connected to a plurality of power sources including. The circuit includes a circuit subassembly coupled to the first power source and a second power source. The circuit subassembly conducts current from the first power source when power is not available from the second power source and otherwise conducts current from the second power source. A first component is coupled to the circuit subassembly and conducts current when the second power source is available; otherwise, it does not conduct current. A second component is coupled to the circuit subassembly and to the first component. The second component conducts current when the first component is conducting current and otherwise does not conduct current. An output lead is coupled to the second component, and the output lead provides a signal indicating the second power source is available.

US Patent:

6560714, May 6, 2003

Filed:

Dec 3, 1999

Appl. No.:

09/454676

Inventors:

Tan Thanh Ho - Santa Clara CA
Scott William Mitchell - San Jose CA
Andrew Nakao - Fremont CA
Ngo Thanh Ho - San Jose CA
George Kwan - Sunnyvale CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 126

US Classification:

713340, 713310

Abstract:

A circuit and method thereof for arbitrating between a plurality of power sources connected to a computer system peripheral device. The circuit includes a first circuit subassembly coupled to a first power source and a second power source. The first circuit subassembly conducts current from the first power source when power is not available from the second power source, and otherwise conducts current from the second power source. The circuit also includes a second circuit subassembly coupled between the first circuit subassembly and a third power source. The second circuit subassembly conducts current from the third power source when the third power source is available and otherwise conducts current from the first circuit subassembly. The second circuit subassembly comprises a first component, a second component and a third component. The first component is coupled to the third power source and the first circuit subassembly.

US Patent:

6564333, May 13, 2003

Filed:

Dec 3, 1999

Appl. No.:

09/454468

Inventors:

Tan Thanh Ho - Santa Clara CA
Scott William Mitchell - San Jose CA
Ryan Hirth - Windsor CA
Ngo Thanh Ho - San Jose CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 126

US Classification:

713340, 713310

Abstract:

A circuit and method thereof for arbitrating between a first power source and a second power source in a computer system peripheral device such as a network adapter (e. g. , a network interface card) that is connected to multiple power sources. The circuit includes a field effect transistor (FET) and a diode integral with the FET coupled between the first power source and the second power source. The FET is adapted to conduct current from the second power source when power is not available from the first power source, and to substantially prevent current from flowing from the first power source to the second power source. The circuit also includes a voltage regulator coupled between the first power source and the second power source, adapted to regulate voltage such that a voltage from the first power source and a voltage from the second power source are approximately equal.

US Patent:

6587488, Jul 1, 2003

Filed:

Nov 8, 2000

Appl. No.:

09/709060

Inventors:

Helmuth E. Meissner - Pleasanton CA
Scott C. Mitchell - Tracy CA

Assignee:

Maxios Laser Corporation - Livermore CA

International Classification:

H01S 313

US Classification:

372 2901, 372 75

Abstract:

Parasitic oscillations are eliminated in solid-state laser components by applying a pattern of grooves to the peripheral sections that do not transmit the desired laser radiation. Additionally, the invention frustrates total internal reflections at polished peripheral component walls by providing a pattern of roughened surface sections in between polished sections. The roughened surfaces may be only microns deep or may be as deep as a few centimeters for large components. The grooves should be sufficiently deep as to inhibit any total internal reflections. The invention applies to all common solid-state architectures that are designed with polished surfaces that do not serve to propagate the desired laser radiation. Examples are slabs, plates, laser rods, waveguides and disks functioning as laser oscillators or amplifiers. The invention is operational with conventional crystal or glass laser hosts or with hosts that are composites of same, similar or dissimilar crystals or glasses.

US Patent:

6751272, Jun 15, 2004

Filed:

Feb 11, 1998

Appl. No.:

09/022069

Inventors:

Lawrence M. Burns - Mountain View CA
Ravi Ramachandran - San Jose CA
David Fisher - Menlo Park CA
Chong Woo - Fremont CA
Scott Mitchell - San Jose CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

H03D 100

US Classification:

375340, 375259

Abstract:

In a system that demodulates a frequency modulated signal using a quadrature detector circuit, an apparatus that tunes the output signal to compensate for any offset in the signal includes an offset adjustment circuit and a control circuit. The offset adjustment circuit is operably coupled to the control circuit which may consist of a DAC and a digital logic such as a computer CPU. The control circuit determines a correction signal in response to a sequence of sampled of the system output, and supplies the correction signal to the offset adjustment circuit. The offset adjustment circuit provides an offset correction signal in response to the correction signal, and combines the offset correction signal with the output of the quadrature detector to provide an offset adjusted signal at an output node.

US Patent:

7166634, Jan 23, 2007

Filed:

Jan 21, 2005

Appl. No.:

11/040923

Inventors:

Scott S. Mitchell - San Carlos CA, US
Kin S. Lam - San Diego CA, US
Jennifer Grodberg - Carlsbad CA, US
Barbara C. Potts - Escondido CA, US
Ginger Tsueng - San Diego CA, US
Donald J. White - San Deigo CA, US
Katherine Anne Reed - San Diego CA, US

Assignee:

Nereus Pharmaceuticals, Inc. - San Diego CA

International Classification:

A01N 43/38
A01N 43/36
C07D 209/10

US Classification:

514414, 548453, 548455

Abstract:

Compounds of Formula I, commonly referred to as bis-indole pyrroles, including isolated naturally-occurring compounds, synthetic and semi-synthetic derivatives thereof having antimicrobial properties and to antimicrobial compositions that include one or more of bis-indole pyrroles and their derivatives or analogs having antimicrobial properties are disclosed. Pharmaceutical compositions comprising such compounds and methods of treating bacterial infections with the disclosed compounds or the disclosed pharmaceutical compositions are also disclosed.

US Patent:

7307998, Dec 11, 2007

Filed:

Aug 27, 2002

Appl. No.:

10/229361

Inventors:

BaoDong Hu - Milpitas CA, US
Scott W. Mitchell - San Jose CA, US

Assignee:

3Com Corporation - Marlborough MA

International Classification:

H04L 12/54

US Classification:

370412, 370419, 370429, 710 52, 711118

Abstract:

A network interface comprises the first port on which incoming data is transmitted and received at the data transfer rate of the network, a buffer memory coupled to the first port, and a second port coupled with the buffer memory, and through which transfer of packets between the host system, and the buffer memory is executed. A driver in the host system allocates a plurality of sets of receive buffers, where each set of receive buffers is composed of receive buffers having different sizes. A receive buffer descriptor cache located at the interface level stores receive buffer descriptors corresponding to receive buffers in the plurality of sets. As incoming packets arrive at the interface, logic determines the size of the incoming packet and assigns the packet to a receive buffer descriptor in the receive buffer descriptor cache according to the determined size. Upload logic at the interface level manages the uploading of packets from the buffer memory to the host system using the assigned receive buffer descriptors. A driver in the host dynamically adjusts the sizes of receive buffers in response to statistics about packet size.

US Patent:

7375129, May 20, 2008

Filed:

Nov 20, 2006

Appl. No.:

11/602869

Inventors:

Scott S. Mitchell - San Carlos CA, US
Kin S. Lam - San Diego CA, US
Jennifer Grodberg - Carlsbad CA, US
Barbara C. Potts - Escondido CA, US
Ginger Tsueng - San Diego CA, US
Donald J. White - San Deigo CA, US
Katherine Anne Reed - San Diego CA, US

Assignee:

Nereus Pharmaceuticals, Inc. - San Diego CA

International Classification:

A61K 31/4025
A61K 31/404
C07D 209/10

US Classification:

514414, 548453, 548455, 514422

Abstract:

Compounds of Formula I, commonly referred to as bis-indole pyrroles, including isolated naturally-occurring compounds, synthetic and semi-synthetic derivatives thereof having antimicrobial properties and to antimicrobial compositions that include one or more of bis-indole pyrroles and their derivatives or analogs having antimicrobial properties are disclosed. Pharmaceutical compositions comprising such compounds and methods of treating bacterial infections with the disclosed compounds or the disclosed pharmaceutical compositions are also disclosed.