Sheng Y Liu

US Patent:

8243737, Aug 14, 2012

Filed:

Mar 22, 2010

Appl. No.:

12/729226

Inventors:

Ting Zhou - Orinda CA, US
Sheng Liu - San Jose CA, US
Ephrem Wu - San Mateo CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370394, 37039541

Abstract:

Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.

US Patent:

8275148, Sep 25, 2012

Filed:

Jul 28, 2009

Appl. No.:

12/510449

Inventors:

Xi-Lin Li - Cupertino CA, US
Sheng Liu - Cupertino CA, US

Assignee:

Fortemedia, Inc. - Sunnyvale CA

International Classification:

H04R 3/00

US Classification:

381 92, 381 93, 704233

Abstract:

An audio processing apparatus is provided, comprising: a main microphone for receiving sounds from a source and noises from non-source sources and generating a main input; a reference microphone for receiving the sounds and the noises and generating a reference input; a short-time Fourier transformation (STFT) unit for applying short time Fourier transformation to convert the main input of a time domain signals into a main signal of a frequency domain and convert the reference input of the time domain signals into a reference signal of the frequency domain; a sensitivity calibrating unit for performing sensitivity calibration on the main signal and the reference signal and generating a main calibrated signal and a reference calibrated signal; and a voice active detector (VAD) for generating a voice active signal according to the main calibrated signal, the reference calibrated signal and a direction of arrival (DOA) signal.

US Patent:

8359466, Jan 22, 2013

Filed:

Apr 29, 2011

Appl. No.:

13/097213

Inventors:

Sheng Liu - Cupertino CA, US
Nikola Radovanovic - Los Altos CA, US
Ephrem Wu - San Mateo CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H04L 29/06
G06F 9/00

US Classification:

713160, 726 14

Abstract:

Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.

US Patent:

8374050, Feb 12, 2013

Filed:

Jun 4, 2011

Appl. No.:

13/153392

Inventors:

Ting Zhou - Orinda CA, US
Ephrem Wu - San Mateo CA, US
Sheng Liu - Cupertino CA, US
Hyuck Jin Kwon - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G11C 8/00
G06F 13/00
G06F 13/28

US Classification:

36523005, 36523003, 711131, 711144, 711149

Abstract:

A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.

US Patent:

8473657, Jun 25, 2013

Filed:

Mar 22, 2010

Appl. No.:

12/729231

Inventors:

Ting Zhou - Orinda CA, US
Sheng Liu - San Jose CA, US
Ephrem Wu - San Mateo CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 3/00
G06F 5/00
G06F 13/00

US Classification:

710111, 710 45, 710 52

Abstract:

Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.

US Patent:

20220299766, Sep 22, 2022

Filed:

Aug 5, 2020

Appl. No.:

17/265457

Inventors:

- Orlando FL, US
- Weifang, Shandong, CN
Sheng Liu - Santa Clara CA, US
Jilin Yang - Santa Clara CA, US

Assignee:

University of Central Florida Research Foundation - Orlando FL
Goertek Inc. - Weifang, Shandong

International Classification:

G02B 27/01
G02B 27/28
G02B 5/30

Abstract:

A head-mounted display apparatus and an optical display system are disclosed. The head-mounted display apparatus comprises: a display assembly, which outputs light of an image; a lens assembly, placed in front of the display assembly to enlarge the image and produce the first aberration of a first direction; and a planar optical assembly, placed between the display assembly and the lens assembly, wherein the planar optical assembly produces the second aberration of a second direction opposite to the first direction to correct the first aberration.

US Patent:

20210089896, Mar 25, 2021

Filed:

Aug 19, 2020

Appl. No.:

16/997917

Inventors:

- Palo Alto CA, US
Camilla Marie Olson - Palo Alto CA, US
Jungah Joo Lee - Oswego OR, US
Sheng Liu - Ann Arbor MI, US

International Classification:

G06N 3/08
G06N 3/04
G06K 9/46
G06K 9/62

Abstract:

An image processing system with a trained neural network examines images to identify design elements present in objects depicted in those images. The image processing system can evaluate a set of images, some of which have been labeled or associated with bins of a set of bins, to identify differences between an actual distribution among the set of bins and a target distribution among the set of bins. From the differences, a second trained neural network, or other computer process, can evaluate the distributions to determine garments or garment features that are underrepresented or overrepresented in the set of images.

US Patent:

20200333262, Oct 22, 2020

Filed:

Jul 2, 2020

Appl. No.:

16/946742

Inventors:

- Milpitas CA, US
Sheng Liu - San Jose CA, US

Assignee:

KLA-Tencor Corporation - Milpitas CA

International Classification:

G01N 21/95
G06T 7/00
G01N 21/956
G01N 21/88

Abstract:

Disclosed is apparatus for inspecting a sample. The apparatus includes illumination optics for simultaneously directing a plurality of incident beams at a plurality of azimuth angles towards a sample and collection optics for directing a plurality of field portions of output light from two or more of the plurality of angles towards two or more corresponding sensors. The two or more sensors are arranged for receiving the field portions corresponding to two or more angles and generating two or more corresponding images. The apparatus further comprises a processor for analyzing the two or more images to detect defects on the sample