Shengnian N Song

US Patent:

6492281, Dec 10, 2002

Filed:

Sep 22, 2000

Appl. No.:

09/668443

Inventors:

Shengnian Song - Austin TX
Bradley Davis - Fukushima, JP

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438715, 438703, 438720, 438687, 438688

Abstract:

Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

US Patent:

7163862, Jan 16, 2007

Filed:

Oct 4, 2005

Appl. No.:

11/243752

Inventors:

Joseph William Wiseman - Austin TX, US
Robert Dawson - Austin TX, US
Shengnian Song - Austin TX, US

Assignee:

Spansion, LLC - Sunnyvale CA

International Classification:

H01L 21/8247

US Classification:

438257, 257E21209

Abstract:

Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.

US Patent:

60227494, Feb 8, 2000

Filed:

Feb 25, 1998

Appl. No.:

9/030742

Inventors:

Bradley M. Davis - Austin TX
Shengnian Davis Song - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 310328

US Classification:

438 14

Abstract:

A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process. The length of time that the superlattice structure is subjected to the process temperature is selected to be the time duration of the process whose temperature is being determined.

US Patent:

61502863, Nov 21, 2000

Filed:

Jan 3, 2000

Appl. No.:

9/477050

Inventors:

Mark I. Gardner - Cedar Creek TX
Shengnian Song - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131
H01L 21469

US Classification:

438791

Abstract:

Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.

US Patent:

62577603, Jul 10, 2001

Filed:

Dec 2, 1999

Appl. No.:

9/454070

Inventors:

Bradley M. Davis - Austin TX
Shengnian Davis Song - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01K 700

US Classification:

374185

Abstract:

A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process. The length of time that the superlattice structure is subjected to the process temperature is selected to be the time duration of the process whose temperature is being determined.

US Patent:

62587307, Jul 10, 2001

Filed:

Feb 9, 1999

Appl. No.:

9/246462

Inventors:

Mark I. Gardner - Cedar Creek TX
Shengnian Song - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131
H01L 21469

US Classification:

438763

Abstract:

A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N. sub. 2 O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N. sub. 2 O plasma is created by applying RF power to a showerhead from which the N. sub. 2 O is dispensed. By reacting an N. sub. 2 O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20. ANG. and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N. sub. 2 O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N. sub. 2 O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N. sub.