Shyam S Krishnamurthy

US Patent:

6339000, Jan 15, 2002

Filed:

Sep 25, 1998

Appl. No.:

09/160834

Inventors:

Surya S. Bhattacharya - Irvine CA
Shyam Krishnamurthy - Los Angeles CA
Hong J. Wu - Irvine CA
Umesh Sharma - Newport Beach CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H01L 21336

US Classification:

438261, 438266, 438287

Abstract:

A method of forming an improved interpoly oxide-nitride-oxide (ONO) stricture in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i. e. , in the context of a memory array embedded in CMOS core technology). This step also tends to encourage formation of a very thin silicon oxynitride layer at the interface of the nitride and TEOS layers, thus helping to cure âpinholesâ typically associated the nitride layer and further increasing the quality and reliability of the ONO structure. The improved interpoly ONO structure is found to show lower leakage current for applied electrice fields between 1 to 15 MV/cm as compared to prior art.

US Patent:

62331787, May 15, 2001

Filed:

Oct 14, 1999

Appl. No.:

9/418399

Inventors:

Shyam Krishnamurthy - Los Angeles CA
Srinjoy Das - Irvine CA
Michael Le - Huntington Beach CA
Frank Van Gieson - Irvine CA
Surya Bhattacharya - Irvine CA
Umesh Sharma - Newport Beach CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G11C 700

US Classification:

36518533

Abstract:

Pre-conditioning method and apparatus for mitigating erase-induced stress within flash memory devices are disclosed. The pre-condition method includes subjecting flash memory cell to a short write process to at least partially discharge the cells. The pre-condition process is applied to an entire sector at one time, and is performed immediately prior to erasing (charging) the cells within the sector.