Stephen Robert Mccormack

US Patent:

6395591, May 28, 2002

Filed:

Dec 7, 2000

Appl. No.:

09/733543

Inventors:

Stephen McCormack - Cupertino CA
Martin Alter - Los Altos CA
Robert S. Wrathall - Scotts Valley CA
Carlos Alberto Laber - Los Altos CA

Assignee:

Micrel, Incorporated - San Jose CA

International Classification:

H01L 218238

US Classification:

438199, 438200, 438222, 438357, 438526, 257357, 257372

Abstract:

An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

US Patent:

20110115019, May 19, 2011

Filed:

Nov 13, 2009

Appl. No.:

12/618546

Inventors:

Frederick Perry Giles - San Jose CA, US
Joel M. McGregor - Nelson, CA
Stephen McCormack - Mountain View CA, US

Assignee:

MAXIM INTEGRATED PRODUCTS, INC. - Sunnyvale CA

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257341, 438283, 257E29261, 257E21417

Abstract:

A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.

US Patent:

56775644, Oct 14, 1997

Filed:

Aug 21, 1996

Appl. No.:

8/736651

Inventors:

Stephen R. McCormack - Colorado Springs CO
Christine H. Chiacchia - Colorado Springs CO
Patrick J. Kelleher - Monument CO

Assignee:

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios Logic Inc. - Fort Collins CO

International Classification:

H01L 2900

US Classification:

257522

Abstract:

The invention concerns fabrication of oxide-filled isolation trenches in integrated circuits. The invention etches a network of trenches in the surface of a uniformly doped wafer which has experienced no substantial processing steps. Such a wafer will have little, if any, surface damage. Such a wafer will etch to the same depth everywhere, because two major factors which affect etching rate are (a) surface damage and (b) doping non-uniformity, and these factors are absent. The trenches are then filled with oxide. They define islands upon which devices (such as transistors) may now be fabricated.

US Patent:

20180286860, Oct 4, 2018

Filed:

Mar 28, 2018

Appl. No.:

15/938887

Inventors:

- San Jose CA, US
Stephen McCormack - Mountain View CA, US
Joel M. McGregor - Nelson, CA

International Classification:

H01L 27/092
H01L 29/10
H01L 29/06
H01L 29/78

Abstract:

A split gate power transistor includes a laterally configured power PMOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.