Subramanian H Krishnamurthy

US Patent:

57617201, Jun 2, 1998

Filed:

Mar 15, 1996

Appl. No.:

8/616540

Inventors:

Subramanian Krishnamurthy - Mountain View CA
James Peterson - Portland OR
Glenn Poole - Fremont CA
Walt Donovan - Milpitas CA

Assignee:

Rendition, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

711140

Abstract:

A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the data caching mechanism includes an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating. Furthermore, the adaptive cache includes an intelligent replacement policy based on a direction in which data is being read from memory as well as the particular mode in which the associated pipeline processor is operating.

US Patent:

57678626, Jun 16, 1998

Filed:

Mar 15, 1996

Appl. No.:

8/616546

Inventors:

Subramanian Krishnamurthy - Mountain View CA
James Peterson - Portland OR
Paul Shupak - San Jose CA

Assignee:

Rendition, Inc. - Sunnyvale CA

International Classification:

G09G 500

US Classification:

345507

Abstract:

A method and an apparatus for writing display data to and reading display data from a FIFO. In one embodiment of the present invention, a memory controller coupled to a memory is configured to retrieve display data from the memory and write the retrieved data to a FIFO. The memory controller retrieves the display data from the memory in response to a FIFO write signal received from an output display controller. The output display controller is further configured to generate a FIFO read signal which is received by the FIFO. In response to the FIFO read signal, display data entries are sequentially read from the FIFO and transferred to an output display. The present invention features a programmable memory circuit such as a register, configured to store the value pointing to a particular display data entry in the FIFO. When the particular display data entry is read, a subsequent FIFO write signal is issued to the memory controller. The value stored in the programmable memory circuit is chosen to minimize the occurrences of overflow and underflow conditions in the FIFO.

US Patent:

61579874, Dec 5, 2000

Filed:

Nov 24, 1997

Appl. No.:

8/976748

Inventors:

Subramanian Krishnamurthy - Mountain View CA
James Peterson - Portland OR
Glenn Poole - Fremont CA
Walt Donovan - Milpitas CA

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1208

US Classification:

711129

Abstract:

A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the disclosed data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the disclosed data caching mechanism features an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating. Furthermore, the adaptive cache disclosed in the present invention features an intelligent replacement policy based on a direction in which data is being read from memory as well as the particular mode in which the associated pipeline processor is operating.