Terence H Chiu

US Patent:

6952750, Oct 4, 2005

Filed:

Sep 27, 2001

Appl. No.:

09/965143

Inventors:

Hugo Cheung - Tucson AZ, US
Lu Yuan - Carlsbad CA, US
Terence Chiu - Tucson AZ, US

Assignee:

Texas Instruments Incoporated - Dallas TX

International Classification:

G06F013/00

US Classification:

710305, 710107, 710 38

Abstract:

The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a bus interface connected to one or more peripheral interface using logic processes to enable microcontroller-based products and other components and devices to achieve a low power data transmission between central processors and peripheral devices. In accordance with an exemplary embodiment, a low power embedded system bus architecture comprises logic devices, for example, an OR gate for passing through only data from a selected peripheral device. To facilitate the throughput of data, the non-selected peripheral devices may only provide logic zero to the OR gate. The logic device arrangement may comprise any combination of logic devices which performs the function of eliminating the need for tristate buffers.

US Patent:

6970951, Nov 29, 2005

Filed:

Oct 2, 2001

Appl. No.:

09/968885

Inventors:

Hugo Cheung - Tucson AZ, US
Terence Chiu - Tucson AZ, US
Lu Yuan - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F003/00

US Classification:

710 14, 710 3, 710 5, 710 38

Abstract:

An external interface for a microprocessor system uses a programmed configuration bit to establish the functionality of a computer port, which improves external interface data transfer speed and input/output power consumption. In particular, the configuration bit allows the microprocessor user to establish the computer port as a memory port, input/output port or the like. The configuration bit is provided to the computer port at system power up or reset. Moreover, the configuration bit may be stored in flash memory and provided to the microprocessor computer port or, in the alternative, the configuration bit may be provided to the computer port directly via the microprocessor bus interface.

US Patent:

7065669, Jun 20, 2006

Filed:

May 6, 2002

Appl. No.:

10/139737

Inventors:

Hugo Cheung - Tucson AZ, US
Lu Yuan - Carlsbad CA, US
Terence Chiu - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/04
G06F 13/00

US Classification:

713600, 711100

Abstract:

A method and apparatus is provided for that includes an improved special function register (SFR) access scheme by using a clock tree distribution process. In accordance with an exemplary embodiment, a conditional SFR write strobe signal may be used to trigger the SFR registers. A clock tree distribution process may be used to achieve significantly higher system speed. When balancing the clock network of the system, the clock leaf of the flip-flop or other circuit element that generates the SFR write strobe signal may be “advanced” by connecting the circuit element directly to the clock root. In addition, the SFR write strobe signal distribution may be balanced as a separate clock tree with minimum insertion delay.

US Patent:

8060929, Nov 15, 2011

Filed:

Sep 21, 2009

Appl. No.:

12/563511

Inventors:

Hugo Cheung - Tucson AZ, US
Lu Yuan - Tucson AZ, US
Terence Chiu - Tucson AZ, US
Bolanle Oladapo Onodipe - Fort Worth TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 7/04

US Classification:

726 17, 726 16, 726 26, 726 27, 713300, 713320

Abstract:

There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.

US Patent:

20020163368, Nov 7, 2002

Filed:

Dec 11, 2001

Appl. No.:

10/014771

Inventors:

Hugo Cheung - Tucson AZ, US
Lu Yuan - Carlsbad CA, US
Terence Chiu - Tucson AZ, US

International Classification:

H03L007/00

US Classification:

327/143000

Abstract:

A method and apparatus is provided for performing an intelligent power-on-reset, and enabling the verification of a current voltage level with a reconfigurable brown out reset voltage level. In addition, the verification process may be selectively bypassed. Furthermore, the flash memory provides storage for the reconfigurable brown out reset voltage level and selected verification process enable/disable signal. In addition, the verification process occurs in a second phase during which some devices are released from reset mode and then those devices control the verification process.

US Patent:

20020166065, Nov 7, 2002

Filed:

May 2, 2002

Appl. No.:

10/137005

Inventors:

Hugo Cheung - Tucson AZ, US
Lu Yuan - Carlsbad CA, US
Terence Chiu - Tucson AZ, US
Bolanle Onodipe - Dallas TX, US

International Classification:

G06F012/14

US Classification:

713/200000, 711/163000

Abstract:

There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.

US Patent:

20020188813, Dec 12, 2002

Filed:

Apr 23, 2002

Appl. No.:

10/128025

Inventors:

Hugo Cheung - Tucson AZ, US
Terence Chiu - Tucson AZ, US
Lu Yuan - Carlsbad CA, US
Russell Anderson - Saint David AZ, US

International Classification:

G06F012/00

US Classification:

711/154000

Abstract:

An on-chip hardware breakpoint generator is disclosed. An embodiment of the present invention is configured to monitor accesses to various memory locations and to produce a breakpoint request when a predetermined memory access occurs. The memory access being monitored can be either a memory read or a memory write. Furthermore, the memory location being monitored can be a program memory location or a data memory location. A system for carrying out the invention may include a comparator coupled to a processor. The comparator is configured to sense when a memory access to a specific location occurs. When such an access occurs, the comparator forwards a signal to a breakpoint generator to implement a breakpoint.

US Patent:

20020194540, Dec 19, 2002

Filed:

Dec 14, 2001

Appl. No.:

10/017179

Inventors:

Hugo Cheung - Tucson AZ, US
Terence Chiu - Tucson AZ, US
Lu Yuan - Tucson AZ, US

International Classification:

H04B001/74

US Classification:

714/034000

Abstract:

The present invention is directed towards a method and system for implementing breakpoints in a processor system for debugging purposes. A separate memory space containing a breakpoint service routine is used and made available to the processor. When a breakpoint request is received, the main memory is switched out in favor of the separate memory space with the breakpoint service routine. The breakpoint service routine is then ran from the separate memory space. Upon the completion of the breakpoint service routine, control of the processor is switched back to the code in the main memory space.