Thomas E Tkacik from 3611 Nambe St, Phoenix, AZ 85044, age 66, Phone: 4807069602

Us Patents

Method For Purchasing Items Over A Non-Secure Communication Channel
view source
US Patent:

6996547, Feb 7, 2006
Filed:

Sep 27, 2000
Appl. No.:

09/671941
Inventors:

Steven R. Tugenberg - Scottsdale AZ, US
Douglas A. Hardy - Scottsdale AZ, US
Thomas E. Tkacik - Phoenix AZ, US
Assignee:

Motorola, Inc. - Schaumburg IL
International Classification:

G06F 17/60
US Classification:

705 77, 705 50, 705 64, 705 52, 713167, 355 52
Abstract:

A method for purchasing items over a non-secure communication channel uses a secure communication device. The secure communication device includes a host processor, a secure memory that includes a laser-scribed encryption key, and a non-secure memory for storing encrypted data. A user's sensitive data is encrypted within the secure memory using the laser-scribed encryption key and stored as encrypted data in the non-secure memory. An encrypted credit card number and an encrypted secret key is retrieved from the non-secure memory, the encrypted credit card and secret key are decrypted with the laser-scribed encryption key, the credit card number is encrypted with a session key, and the encrypted credit card number is transferred over the network to a destination such as an internet vendor.

Secure Memory And Processing System Having Laser-Scribed Encryption Key
view source
US Patent:

7103782, Sep 5, 2006
Filed:

Sep 27, 2000
Appl. No.:

09/671949
Inventors:

Steven R. Tugenberg - Scottsdale AZ, US
Douglas A. Hardy - Scottsdale AZ, US
Thomas E. Tkacik - Phoenix AZ, US
Assignee:

Motorola, Inc. - Schaumburg IL
International Classification:

H04L 9/32
G06F 11/30
G06F 17/30
US Classification:

713194, 713193, 726 3, 726 26, 380201, 380203
Abstract:

A secure memory and processing system is disclosed for use in various types of communication devices. The secure processing system provides for the encryption and storage of sensitive data in a storage medium external to the secure processing system. The encrypted data is decrypted with encryption logic circuitry within the secure memory and transferred to a zeroizable memory for use by a host processor. The secure memory uses a laser-scribed encryption key coupled to encryption logic circuitry within the secure memory for encrypting and decrypting the sensitive information.

Method And Apparatus For Providing Security For Debug Circuitry
view source
US Patent:

7248069, Jul 24, 2007
Filed:

Aug 11, 2003
Appl. No.:

10/638795
Inventors:

William C. Moyer - Dripping Springs TX, US
Thomas E. Tkacik - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H03K 19/00
H04L 9/00
US Classification:

326 16, 714724, 713168
Abstract:

The invention relates to debug circuitry () and more particularly to a method and apparatus for providing security for debug circuitry (). In one embodiment, a plurality of non-volatile elements () are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.

Autonomous Memory Checker For Runtime Security Assurance And Method Therefore
view source
US Patent:

7401234, Jul 15, 2008
Filed:

Mar 1, 2004
Appl. No.:

10/791171
Inventors:

Lawrence L. Case - Phoenix AZ, US
Mark D. Redman - Gilbert AZ, US
Thomas E. Tkacik - Phoenix AZ, US
Joel D. Feldman - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

G06F 11/30
US Classification:

713193, 713153, 711100, 711170, 711137, 707 9, 717151
Abstract:

Methods and apparatus are provided for an electronic device having an autonomous memory checker for runtime security assurance. The autonomous memory checker comprises a controller, a memory reference file coupled to the controller, and an authentication engine coupled to the controller. A check is performed during runtime operation of the electronic device. The autonomous memory checker generates runtime reference values corresponding to trusted information stored in memory. The runtime reference values are compared against memory reference values stored in the memory reference file. The memory reference values are generated from the trusted information stored in memory. An error signal is generated when the runtime reference values are not identical to the memory reference values thereby indicating that the trusted information has been modified.

Queued Interface Devices, Multi-Core Peripheral Systems, And Methods For Sharing A Peripheral In A Multi-Core System
view source
US Patent:

7512723, Mar 31, 2009
Filed:

Dec 29, 2006
Appl. No.:

11/647653
Inventors:

Thomas E. Tkacik - Phoenix AZ, US
Matthew W. Brocker - Chandler AZ, US
Lawrence L. Case - Phoenix AZ, US
Erik D. Swanson - Mesa AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

G06F 3/00
US Classification:

710 33, 710309, 710113, 710120
Abstract:

A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.

Method And Apparatus For Providing Security In A Data Processing System
view source
US Patent:

7542567, Jun 2, 2009
Filed:

Jun 10, 2004
Appl. No.:

10/865267
Inventors:

Michael J. Torla - Chandler AZ, US
Thomas E. Tkacik - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H04L 9/00
US Classification:

380 44, 713189, 713153
Abstract:

One embodiment relates to a data processing system having a cryptographic unit. The cryptographic unit includes cryptographic circuitry which performs a first cryptographic function to provide security for a portion of the cryptographic unit, and which performs a second cryptographic function to provide security for a portion of the data processing system external to the cryptographic unit. The cryptographic unit may therefore operate in a normal operating mode and in a secure operating mode. During a first secure operating mode a first key is used to decrypt first security configuration information which includes a second key. During a second secure operating mode, the second key is used to decrypt second security configuration information. The cryptographic unit may include a secure internal memory such that during the secure operating modes, the cryptographic unit may only process descriptors provided from this secure internal memory.

Method And Apparatus For Secure Scan Testing
view source
US Patent:

7725788, May 25, 2010
Filed:

Jan 25, 2007
Appl. No.:

11/627229
Inventors:

Thomas Tkacik - Phoenix AZ, US
Jonathan Lutz - Kitchner, CA
Lawrence Case - Fountain Hills AZ, US
Douglas Hardy - Scottsdale AZ, US
Mark Redman - Gilbert AZ, US
Gregory Schmidt - Chandler AZ, US
Steven Tugenberg - Scottsdale AZ, US
Michael D. Fitzsimmons - Austin TX, US
Darrell L. Carder - Dripping Springs TX, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

G01R 31/28
US Classification:

714726
Abstract:

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

Method And Apparatus For Increasing Security In A System Using An Integrated Circuit
view source
US Patent:

7969179, Jun 28, 2011
Filed:

Mar 31, 2009
Appl. No.:

12/414752
Inventors:

Thomas E. Tkacik - Phoenix AZ, US
Asaf Ashkenazi - San Diego CA, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H03K 19/00
US Classification:

326 8
Abstract:

An integrated circuit can be made more secure by programming a one time programmable circuit so that different signals are provided on terminals as compared to when the integrated circuit was not secure. Instead, or in addition, the integrated circuit can be made more secure by providing decode circuitry that can be used with the one time programmable circuit to select different internal address maps in response to an address value. The decode circuitry can use a first address map when the integrated circuit is secure, and a different address map when the integrated circuit is non-secure.