Todd Michael Mitchell

US Patent:

6690083, Feb 10, 2004

Filed:

Jun 1, 2000

Appl. No.:

09/586411

Inventors:

Todd Mitchell - San Antonio TX
Mark W. Haley - Rio Medina TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2900

US Classification:

257538, 257536, 257537, 257516, 257518

Abstract:

The present invention is drawn to a method and a system for creating a sub-1V bandgap reference (BGR) circuit. In particular, a sub-1V BGR circuit is formed comprising a shallow trench isolation (STI) region and a poly silicon region above said STI region. The poly silicon region is formed having a first doped region longer than a second doped region. The poly silicon region as one single structure is adapted to function as a resistor and a diode coupled in series, said structure adapted to generate currents in a feedback loop to generate a BGR voltage. In forming the sub-1V BGR circuit, a silicide blocking mask (already available in the process flow for forming a standard semiconductor device) is used to prevent spacer oxide from forming above the center portion of the poly silicon region. In turn, silicide contacts can be formed away from the center portion of the poly silicon region.

US Patent:

63067463, Oct 23, 2001

Filed:

Dec 30, 1999

Appl. No.:

9/475698

Inventors:

Mark W. Haley - Rio Medina TX
Todd Mitchell - San Antonio TX

Assignee:

Koninklijke Philips Electronics - Eindhoven

International Classification:

H01L 2144

US Classification:

438601

Abstract:

The present invention is directed to a method of forming an insulative layer over a fuse link in a semiconductor device that is sufficiently thick to encapsulate the fuse link during laser opening, thereby preventing vaporized metal from re-depositing on the fuse link. The layer is also sufficiently thin to allow the laser to penetrate the insulative layer during laser opening of the fuse. A primary dielectric layer is formed over a metal fuse link, the primary dielectric having a predetermined deposition thickness over the fuse link. The primary dielectric layer is then covered with an etch interrupting layer. The etch interrupting layer is covered with a secondary dielectric layer and a portion of the secondary dielectric layer is then removed, resulting in an interlayer dielectric (ILD) stack formed from the etch interrupting layer and the remaining secondary dielectric layer. The ILD has a selected thickness that is greater than the thickness of the primary dielectric layer. A metal layer is formed over the interlayer dielectric and then the layers over the etch interrupting layer and above the metal fuse link are then removed.