Tri Cao Ngo

US Patent:

20180149698, May 31, 2018

Filed:

May 11, 2017

Appl. No.:

15/592602

Inventors:

- Hsinchu, TW
Abhishek KONERU - Hsinchu City, TW
Tri NGO - San Jose CA, US
Yun-Han LEE - Hsinchu County, TW

International Classification:

G01R 31/3185
G01R 31/3181
G01R 31/3177

Abstract:

A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.