Tyler M Lowrey

US Patent:

6356495, Mar 12, 2002

Filed:

Mar 12, 2001

Appl. No.:

09/804617

Inventors:

Tyler A. Lowrey - Sandpoint ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1300

US Classification:

365203, 36518909

Abstract:

A dynamic random access memory includes a plate line; a digit line; a memory cell selectively coupled between the digit line and the plate line; sense circuitry selectively coupled to the memory cell to read the memory cell and capable of applying a first voltage from the plate line to the digit line; equilibration circuitry selectively coupling the plate line to an equilibration voltage less than the first voltage and selectively coupling the digit line to the equilibration voltage; and control circuitry configured to cause the equilibration circuitry to couple the plate line to the equilibration voltage while the memory cell is being accessed. A method of manufacturing a dynamic random access memory includes providing control circuitry configured to operate in a specified manner. A method of operating a dynamic random access memory includes turning on one equilibration transistor, while another equilibration transistor is off, so that a plate line equilibrates to a voltage defined by the equilibration voltage source during accessing of a memory cell.

US Patent:

6406954, Jun 18, 2002

Filed:

Sep 2, 1999

Appl. No.:

09/388559

Inventors:

Shubneesh Batra - Boise ID
Luan C. Tran - Meridian ID
Tyler A. Lowrey - Sandpoint ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218238

US Classification:

438199, 438542, 438672

Abstract:

In one aspect, the invention includes a semiconductor processing method of diffusing dopant into both n-type and p-type doped regions of a semiconductive substrate. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A mask material is formed over the p-type and n-type doped portions. A first opening is formed to extend through the mask material and to the n-type doped portion. A second opening is formed to extend through the mask material and to the p-type doped portion. Conductively doped polysilicon is formed within the first and second openings. Dopant is out-diffused from the conductively-doped polysilicon and into the n-type and p-type doped portions. In another aspect, the invention includes methods of forming CMOS constructions.

US Patent:

6423620, Jul 23, 2002

Filed:

Aug 21, 2001

Appl. No.:

09/935474

Inventors:

Pai-Hung Pan - Boise ID
Luan C. Tran - Meridian ID
Tyler A. Lowrey - Sandpoint ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438597, 438239

Abstract:

Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

US Patent:

6599800, Jul 29, 2003

Filed:

Sep 14, 2001

Appl. No.:

09/954340

Inventors:

Tyler A. Lowrey - Sandpoint ID
Luan C. Tran - Meridian ID
Alan R. Reinberg - Westport CT
Mark Durcan - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

A01L 218242

US Classification:

438254, 438253, 438250, 438396, 438397, 438393

Abstract:

Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

US Patent:

6600190, Jul 29, 2003

Filed:

Dec 5, 2000

Appl. No.:

09/730865

Inventors:

Tyler A. Lowrey - Sandpoint ID
Luan C. Tran - Meridian ID
Alan R. Reinberg - Westport CT
D. Mark Durcan - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27108

US Classification:

257306, 257309

Abstract:

Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

US Patent:

6995059, Feb 7, 2006

Filed:

Jul 25, 2003

Appl. No.:

10/627468

Inventors:

Tyler A. Lowrey - Sandpoint ID, US
Luan C. Tran - Meridian ID, US
Alan R. Reinberg - Westport CT, US
Mark Durcan - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/8242

US Classification:

438254, 438253, 438250, 438396, 438397, 438393

Abstract:

Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

US Patent:

20060208282, Sep 21, 2006

Filed:

May 15, 2006

Appl. No.:

11/434303

Inventors:

Luan Tran - Meridian ID, US
D. Duncan - Boise ID, US
Tyler Lowrey - Sandpoint ID, US
Rob Kerr - Boise ID, US
Kris Brown - Garden City ID, US

International Classification:

H01L 27/10
H01L 21/82

US Classification:

257206000, 438128000, 257208000, 257E27108

Abstract:

A memory device includes memory cells, bit lines, active areas, and transistors formed in each active area and electrically coupling memory cells to corresponding bit lines. The memory cells can have an area of about 6F, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line may include a first level portion and a second level portion.

US Patent:

62466046, Jun 12, 2001

Filed:

Jul 14, 1999

Appl. No.:

9/353307

Inventors:

Tyler A. Lowrey - Sandpoint ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1124

US Classification:

365149

Abstract:

A dynamic random access memory includes a plate line; a digit line; a memory cell selectively coupled between the digit line and the plate line; sense circuitry selectively coupled to the memory cell to read the memory cell and capable of applying a first voltage from the plate line to the digit line; equilibration circuitry selectively coupling the plate line to an equilibration voltage less than the first voltage and selectively coupling the digit line to the equilibration voltage; and control circuitry configured to cause the equilibration circuitry to couple the plate line to the equilibration voltage while the memory cell is being accessed. A method of manufacturing a dynamic random access memory includes providing control circuitry configured to operate in a specified manner. A method of operating a dynamic random access memory includes turning on one equilibration transistor, while another equilibration transistor is off, so that a plate line equilibrates to a voltage defined by the equilibration voltage source during accessing of a memory cell.