Synopsys
Manager I, R and D
Synopsys Apr 2011 - Jun 2013
R and D Engineer, Senior I
Synopsys Apr 2011 - Jun 2013
Supervisor Ii, R and D
Synopsys Jun 2008 - Apr 2011
R and D Engineer Ii
Synopsys Aug 2007 - Jun 2008
R and D Engineer I
Education:
State Engineering University of Armenia 2008 - 2011
State Engineering University of Armenia 2006 - 2008
Masters, Design
State Engineering University of Armenia 2002 - 2006
Bachelors
Skills:
Eda Tcl Debugging Verilog Physical Design Static Timing Analysis Algorithms Asic Perl Formal Verification Primetime Physical Verification Timing Closure Drc Lvs Logic Synthesis Floorplanning Gnu Make Clock Tree Synthesis Parasitic Extraction Dft Digital Electronics Csh Timing Signal Integrity Spice Hercules Soc Vlsi Integrated Circuit Design Ic Semiconductors Cmos
Interests:
Children Analog Sound Effects Environment Science and Technology Music Drummer Arts and Culture Health