Vijay S Menon

US Patent:

7913236, Mar 22, 2011

Filed:

Sep 29, 2006

Appl. No.:

11/540817

Inventors:

Ali-Reza Adl-tabatabai - Santa Clara CA, US
Vijay Menon - Seattle WA, US
Richard L. Hudson - Florence MA, US
Bratin Saha - San Jose CA, US
Tatiana Shpeisman - Menlo Park CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717140, 717148, 717151

Abstract:

A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Other embodiments are disclosed and claimed.

US Patent:

8065491, Nov 22, 2011

Filed:

Dec 30, 2007

Appl. No.:

11/967232

Inventors:

Tatiana Shpeisman - Menlo Park CA, US
Ali-Reza Adl-Tabatabai - Santa Clara CA, US
Vijay Menon - Seattle WA, US
Bratin Saha - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711152, 711154, 711E12001

Abstract:

A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.

US Patent:

8364911, Jan 29, 2013

Filed:

Jul 13, 2011

Appl. No.:

13/182162

Inventors:

Tatiana Shpeisman - Menlo Park CA, US
Ali-Reza Adl-Tabatabai - Santa Clara CA, US
Vijay Menon - Seattle WA, US
Bratin Saha - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/14

US Classification:

711152, 710200

Abstract:

A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.

US Patent:

8612950, Dec 17, 2013

Filed:

Jun 19, 2008

Appl. No.:

12/142102

Inventors:

Tatiana Shpeisman - Menlo Park CA, US
Vijay Menon - Seattle WA, US
Ali-Reza Adl-Tabatabai - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717151, 717153, 717155, 717156

Abstract:

A method and apparatus for dynamic optimization of strong atomicity barriers is herein described. During runtime compilation, code including non-transactional memory accesses that are to conflict with transactional memory accesses is patched to insert transactional barriers at the conflicting non-transactional memory accesses to ensure isolation and strong atomicity. However, barriers are omitted or removed from non-transactional memory accesses that do not conflict with transactional memory accesses to reduce barrier execution overhead.

US Patent:

20050055516, Mar 10, 2005

Filed:

Sep 10, 2003

Appl. No.:

10/658897

Inventors:

Vijay Menon - Seattle WA, US
Brian Murphy - Mountain View CA, US
Ali-Reza Adl-Tabatabai - Santa Clara CA, US
Tatiana Shpeisman - Menlo Park CA, US

International Classification:

G06F012/00

US Classification:

711158000, 711167000

Abstract:

According to one embodiment a computer method and apparatus for causing a computer to perform a speculative read re-ordered load is disclosed. A speculative read re-ordered load instruction is inserted into the instruction sequence to optimize the code. Memory conflict information representing the speculative read re-ordered load is stored. When a later potentially conflicting load is executed, its physical address is matched against the physical address of the stored memory conflict information. If the potentially conflicting load has a matching physical address and a different value than the stored memory conflict information representing the speculative read re-ordered load, then the stored memory conflict information is invalidated.

US Patent:

20070006187, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/172675

Inventors:

Brian Murphy - Beijing, CN
Vijay Menon - Seattle WA, US
Tatiana Shpeisman - Menlo Park CA, US
Leaf Petersen - San Jose CA, US

International Classification:

G06F 9/45

US Classification:

717140000

Abstract:

A compiler can perform aggressive code motion optimization by respecting value dependence of safety values inserted into the intermediate representation of a computer program. In one embodiment, the present invention includes converting a computer program into an intermediate representation, the intermediate representation containing at least one safety check ensuring the safety of at least one dangerous instruction. In one embodiment, the invention further includes defining a safety value in the intermediate representation as the safety check and including the safety value as a safety argument of the dangerous instruction. In one embodiment, it is determined that the safety check is redundant. In response, in one embodiment, the invention includes updating the safety argument of the dangerous instruction, and eliminating the safety check from the intermediate representation during the safety check elimination optimization. Other embodiments are described and claimed.

US Patent:

20070006197, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/172676

Inventors:

Brian Murphy - Beijing, CN
Vijay Menon - Seattle WA, US
Tatiana Shpeisman - Menlo Park CA, US
Leaf Peterson - San Jose CA, US

International Classification:

G06F 9/45

US Classification:

717151000

Abstract:

Optimized intermediate representation of a computer program can be verified using safety values. In one embodiment, the invention includes receiving an optimized intermediate representation of a computer program, the intermediate representation including a plurality of safety values representing safety dependencies, and verifying the safety of the computer program by checking value dependence between the plurality of safety values. Other embodiments are described and claimed.

US Patent:

20100162249, Jun 24, 2010

Filed:

Dec 24, 2008

Appl. No.:

12/344144

Inventors:

Tatiana Shpeisman - Menlo Park CA, US
Ali-Reza Adl-Tabatabai - San Jose CA, US
Vijay Menon - Seattle WA, US

International Classification:

G06F 9/46

US Classification:

718101

Abstract:

A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.