Vijay K Singh

US Patent:

7920489, Apr 5, 2011

Filed:

Sep 14, 2007

Appl. No.:

11/855818

Inventors:

Vijay Singh - Sunnyvale CA, US

Assignee:

Net App, Inc. - Sunnyvale CA

International Classification:

H04B 1/56

US Classification:

370276, 370356, 709215

Abstract:

Embodiments herein provide full duplex operation (i. e. , simultaneous receiving and transmitting of data over a network) of a network device of a computer system. Receiving and transmitting threads are used for receiving and transmitting data using the network device, the threads requiring access to an associated data structure to use the network device. Conventionally, the data structure is locked to allow access to only one thread at a time to protect against information inconsistencies in the data structure. Some embodiments remove the locking feature of the data structure to provide simultaneous access to the data structure by the receiving and transmitting threads, and thus allow full duplex operation of the network device. Protections against information inconsistencies in the data structure may be provided, including providing separate receiving and transmitting information sections in the data structure and assurances that only one transmitting thread accesses the data structure at any time.

US Patent:

8252437, Aug 28, 2012

Filed:

Oct 28, 2010

Appl. No.:

12/914647

Inventors:

Vijay Prakash Singh Rawat - San Jose CA, US
Kurt Allan Rubin - San Jose CA, US

Assignee:

Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam

International Classification:

G11B 5/66

US Classification:

428826

Abstract:

A magnetic recording disk has surface features of elevated lands and recessed grooves, and a planarized upper surface. A chemical-mechanical-polishing (CMP) stop layer is deposited over the lands and into the recesses. An adhesion film, like silicon, is deposited over the CMP stop layer, and fill material containing a silicon oxide (SiO) is deposited over and in contact with the adhesion film. The adhesion film improves the adhesion of the SiOfill material and prevents delamination during a subsequent two-step CMP planarizing process.

US Patent:

8566833, Oct 22, 2013

Filed:

Mar 11, 2008

Appl. No.:

12/045991

Inventors:

Anumita Biswas - Santa Clara CA, US
Vijay Singh - Sunnyvale CA, US
Sonny Son - Cambell CA, US
Bill Berryman - Sunnyvale CA, US
Dave Noveck - Lexington MA, US
Peter Shah - Waltham MA, US
Jason Goldschmidt - Brookline MA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 9/50

US Classification:

718104, 709213, 709226, 718102

Abstract:

According to a novel mechanism, each processing device (e. g. , a central processing unit (CPU) in a multi-processor system) is assigned to process a single execution thread for a task and the execution thread is processed across various layers of the multi-processor system (such as a network layer and application layer) without being divided into separate threads. Advantageously, upon initialization of the multi-processor system, network context data structures are created equal to the number of processing devices in the system. As used herein, a network context is a logical entity to which zero or more connections are bound during their lifetime. Rather than sharing data structures among execution threads, a multi-processor system allocates memory resources per each network context during initialization of the system. As a result, an execution thread processing a task queued to a particular network context accesses memory resources allocated for that network context only.

US Patent:

20140005974, Jan 2, 2014

Filed:

Jun 28, 2013

Appl. No.:

13/930173

Inventors:

Vijay Singh - Fremont CA, US
Nataraj Paila - Fremont CA, US
Scott Glaser - Dublin CA, US

International Classification:

G06F 11/263

US Classification:

702123

Abstract:

A system and method for configuring a test for a program is provided. The method, for example, may include receiving, by a processor, an identification of an electronic device, retrieving, by the processor, a configuration of the electronic device from a memory, modifying, by the processor, at least one step of the test based upon the configuration of the electronic device.

US Patent:

20200081807, Mar 12, 2020

Filed:

Nov 13, 2019

Appl. No.:

16/681979

Inventors:

- Sunnyvale CA, US
Vijay Singh - San Jose CA, US

International Classification:

G06F 11/20
G06F 11/07

Abstract:

One or more techniques and/or computing devices are provided for automatic switchover implementation. For example, a first storage controller, of a first storage cluster, may have a disaster recovery relationship with a second storage controller of a second storage cluster. In the event the first storage controller fails, the second storage controller may automatically switchover operation from the first storage controller to the second storage controller for providing clients with failover access to data previously accessible to the clients through the first storage controller. The second storage controller may detect, cross-cluster, a failure of the first storage controller utilizing remote direct memory access (RDMA) read operations to access heartbeat information, heartbeat information stored within a disk mailbox, and/or service processor traps. In this way, the second storage controller may efficiently detect failure of the first storage controller to trigger automatic switchover for non-disruptive client access to data.

US Patent:

20190378539, Dec 12, 2019

Filed:

Aug 26, 2019

Appl. No.:

16/551671

Inventors:

- San Jose CA, US
Vijay Prakash Singh RAWAT - San Jose CA, US
Barry C. STIPE - San Jose CA, US

International Classification:

G11B 5/60
G11B 5/31

Abstract:

Embodiments disclosed herein generally relate to a HAMR head. The HAMR head includes a main pole, a waveguide and a NFT disposed between the main pole and the waveguide. The NFT includes an antenna, and the antenna includes a first portion and a second portion. The second portion may be made of a material having a higher melting point than the material of the first portion. Having the second portion helps reduce the temperature rise of the NFT and reduce the laser power applied to the NFT.

US Patent:

20190324787, Oct 24, 2019

Filed:

Jun 28, 2019

Appl. No.:

16/456846

Inventors:

- Sunnyvale CA, US
Kazunobu Nishime - Milpitas CA, US
Pankti Vinay Majmudar - Sunnyvale CA, US
Prachi Bapurao Deshmukh - San Jose CA, US
Susan M. Coatney - Cupertino CA, US
Vijay Singh - San Jose CA, US

International Classification:

G06F 9/455
G06F 3/06
G06F 11/14

Abstract:

One or more techniques and/or devices are provided for storage virtual machine relocation (e.g., ownership change) between storage clusters. For example, operational statistics of a first storage cluster and a second storage cluster may be evaluated to identify a set of load balancing metrics. Ownership of one or more storage aggregates and/or one or more storage virtual machines may be changed (e.g., permanently changed for load balancing purposes or temporarily changed for disaster recovery purposes) between the first storage cluster and the second storage cluster utilizing zero-copy ownership change operations based upon the set of load balancing metrics. For example, if the first storage cluster is experiencing a relatively heavier load of client I/O operations and the second storage cluster has available resources, ownership of a storage aggregate and a storage virtual machine may be switched from the first storage cluster to the second storage cluster for load balancing.

US Patent:

20190284619, Sep 19, 2019

Filed:

May 30, 2019

Appl. No.:

16/426529

Inventors:

- Grand Cayman, KY
Vijay SINGH - Union City CA, US

International Classification:

C12Q 1/6834
C07H 21/04

Abstract:

The present disclosure relates to processes for inverting oligonucleotide probes in an in situ synthesized array. These processes can be used to reverse the orientation of probes with respect to the substrate from 3′-bound to 5′-bound. These processes can also be used to reduce or eliminate the presence of truncated probe sequences from an in situ synthesized array.