Wei Xia

US Patent:

8178944, May 15, 2012

Filed:

Jun 22, 2009

Appl. No.:

12/456833

Inventors:

Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/00

US Classification:

257529, 257209, 257E23149

Abstract:

According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

US Patent:

8269275, Sep 18, 2012

Filed:

Oct 21, 2009

Appl. No.:

12/589357

Inventors:

Xiangdong Chen - Irvine CA, US
Wei Xia - Irvine CA, US
Henry Kuo-Shun Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/78

US Classification:

257336, 257343, 257344, 257E29256, 438286, 438201, 438202

Abstract:

According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

US Patent:

8455977, Jun 4, 2013

Filed:

May 8, 2012

Appl. No.:

13/466986

Inventors:

Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/00

US Classification:

257529, 257209, 257E23149

Abstract:

According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

US Patent:

8497564, Jul 30, 2013

Filed:

Aug 13, 2009

Appl. No.:

12/583016

Inventors:

Xiangdong Chen - Irvine CA, US
Wei Xia - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/92
H01L 21/02

US Classification:

257532

Abstract:

According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

US Patent:

8502320, Aug 6, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/250563

Inventors:

Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 21/70

US Classification:

257368, 257E21632, 438200

Abstract:

A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

US Patent:

8558300, Oct 15, 2013

Filed:

Nov 6, 2009

Appl. No.:

12/590370

Inventors:

Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Frank Hui - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/788

US Classification:

257316, 257412

Abstract:

According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

US Patent:

8570811, Oct 29, 2013

Filed:

Aug 26, 2011

Appl. No.:

13/219414

Inventors:

Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 11/34

US Classification:

36518524, 36518514, 36518528, 36518521

Abstract:

According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.

US Patent:

8614497, Dec 24, 2013

Filed:

Aug 7, 2009

Appl. No.:

12/462692

Inventors:

Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 29/92

US Classification:

257532, 257E29343

Abstract:

According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.