Wing F Liu

US Patent:

6583656, Jun 24, 2003

Filed:

Aug 21, 2002

Appl. No.:

10/064831

Inventors:

Wing Faat Liu - San Jose CA

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03K 512

US Classification:

327170, 327108, 326 27

Abstract:

A differential clock driver uses feedback to reduce timing skews between the true and complement differential outputs. Each of the differential outputs has a pull-up driver and a pull-down driver. Each pull-up or pull-down driver has an initial transistor and a final transistor in parallel to drive the output. A resistor separates gates of the initial and final transistors, causing a delay to enable the final transistor. A transmission gate provides feedback from the other output to the gate of the final transistor. When the other output is faster that the output being driven, the transmission gate transfers charge from the other output to the gate of the final transistor, causing it to speed up driving its output. This helps compensates for the timing skew between the outputs. Skews present on differential inputs can be compensated by the transmission gate feedback.

US Patent:

6750357, Jun 15, 2004

Filed:

Jun 25, 1999

Appl. No.:

09/344226

Inventors:

Ronald H. Chiarello - Castro Valley CA
Wing Liu - Belmont CA
Kathy E. Yokobata - Sunnyvale CA

Assignee:

SynGen, Inc. - San Carlos CA

International Classification:

C07D31178

US Classification:

549394, 436172, 436800

Abstract:

Fluorescent dyes based on rhodamine are derivatized to form labeled conjugates that fluoresce upon excitation with light of an appropriate wavelength. Particularly preferred embodiments are certain single isomer form rhodamine phosphoramidites. These rhodamine phosphoramidites enhance the efficiency of synthesizing rhodamine-labeled oligonucleotides by solid phase methods. Conjugate embodiments of the invention are prevented from being converted to a non-fluorescent lactam form due to having a fully substituted amide linkage derived from the 3-position carboxylate.

US Patent:

7002422, Feb 21, 2006

Filed:

Apr 1, 2004

Appl. No.:

10/708939

Inventors:

Wing Faat Liu - San Jose CA, US

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03B 5/32

US Classification:

331158, 331116 FE, 331116 R

Abstract:

An oscillator inverter circuit has an input at a first crystal node and drives a second crystal node of a crystal oscillator. The first node is lightly loaded by a gate of an input transistor that generates a buffered node. The buffered node voltage is converted to a varying current by a converter transistor. Another varying current through upper and lower amplifier transistors are mirrored to upper and lower current mirror transistors. The gate and drain of the lower current mirror transistor are connected to the gate of an output transistor that pulls down the second node with low impedance. The drain of the upper current mirror transistor diverts current from an output current source, changing pull-up current to the second node through a p-channel transistor. An input resistor between the first node and the buffered node provides a DC bias but blocks AC oscillation signals.

US Patent:

7002423, Feb 21, 2006

Filed:

Jul 20, 2004

Appl. No.:

10/710549

Inventors:

Boris Drakhlis - Mountain View CA, US
Wing Faat Liu - San Jose CA, US
Craig M. Taylor - Pleasanton CA, US
Tony Yeung - Milpitas CA, US

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03B 5/32

US Classification:

331158, 331116 R, 331116 FE, 331 74, 331107 A

Abstract:

A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc)×(Xc) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc and Xc are the effective capacitive reactances of phase-shift legs at nodes X and X. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

US Patent:

7265620, Sep 4, 2007

Filed:

Jul 6, 2005

Appl. No.:

11/160730

Inventors:

Wing Faat Liu - San Jose CA, US
Michael Y. Zhang - Palo Alto CA, US

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03F 3/45

US Classification:

330253

Abstract:

An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.

US Patent:

7332977, Feb 19, 2008

Filed:

Dec 21, 2005

Appl. No.:

11/306262

Inventors:

Boris Drakhlis - Mountain View CA, US
Wing Faat Liu - San Jose CA, US
Craig M. Taylor - Pleasanton CA, US
Tony Yeung - Milpitas CA, US

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03B 27/00

US Classification:

331 46, 331 49, 331 53, 331158, 331116 R, 331116 FE, 331 74

Abstract:

A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc)×(Xc) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc and Xc are the effective capacitive reactances of phase-shift legs at nodes X and X. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

US Patent:

8442106, May 14, 2013

Filed:

Jul 13, 2010

Appl. No.:

12/834913

Inventors:

Wing Faat Liu - Milpitas CA, US
Freeman Y. Zhong - San Ramon CA, US
Lizhi Zhong - Sunnyvale CA, US
Eric Zhang - Fremont CA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

H04L 27/01

US Classification:

375233, 375234

Abstract:

An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

US Patent:

20210226639, Jul 22, 2021

Filed:

Apr 5, 2021

Appl. No.:

17/222667

Inventors:

- Cupertino CA, US
Wenbo Liu - Cupertino CA, US
Wing Liu - Milpitas CA, US
Sanjeev K. Maheshwari - Fremont CA, US
Vishal Varma - Fremont CA, US
Sunil Bhosekar - Austin TX, US
Lizhi Zhong - Sunnyvale CA, US
Gary A. Rogan - Los Altos CA, US

International Classification:

H03L 7/081
H03L 7/08

Abstract:

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.