Xiao Qing Liu

US Patent:

7067902, Jun 27, 2006

Filed:

Dec 2, 2003

Appl. No.:

10/726140

Inventors:

Habib Hichri - Wappingers Falls NY, US
Xiao H. Liu - Croton On Hudson NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Conal E. Murray - Yorktown Heights NY, US
Jawahar P. Nayak - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/40

US Classification:

257621, 438622

Abstract:

Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

US Patent:

7276787, Oct 2, 2007

Filed:

Dec 5, 2003

Appl. No.:

10/729254

Inventors:

Daniel Charles Edelstein - White Plains NY, US
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Sherif A. Goma - Hawthorne NY, US
Raymond R. Horton - Dover Plains NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Xiao Hu Liu - Croton on Hudson NY, US
Chirag Suryakant Patel - Peekskill NY, US
Edmund Juris Sprogis - Underhill VT, US
Michelle Leigh Steen - Danbury CT, US
Brian Richard Sundlof - Beacon NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
George Frederick Walker - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/498
H01L 21/4763
H01L 29/40
H01L 23/52

US Classification:

257698, 257E23067, 257E23075, 257E23011, 257E25013, 257E21597, 257E23006, 257E23172, 257E23174, 257774, 257773, 257702, 257680, 257700, 257758

Abstract:

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

US Patent:

7371684, May 13, 2008

Filed:

May 16, 2005

Appl. No.:

11/130078

Inventors:

Matthew Earl Colburn - Hopewell Junction NY, US
Ricardo Alves Donaton - Cortlandt Manor NY, US
Conal E. Murray - Yorktown Heights NY, US
Satyanarayana Venkata Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Theodorus Eduardus Fransiscus Maria Standaert - Pine Bush NY, US
Xiao Hu Liu - Briarcliff Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302

US Classification:

438689, 438622, 438637, 438694, 216 13, 216 41

Abstract:

A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

US Patent:

7394089, Jul 1, 2008

Filed:

Aug 25, 2006

Appl. No.:

11/467294

Inventors:

James P. Doyle - Bronx NY, US
Bruce G. Elmegreen - Golden Bridge NY, US
Lia Krusin-Elbaum - Dobbs Ferry NY, US
Chung Hon Lam - Peekskill NY, US
Xiao Hu Liu - Briarcliff Manor NY, US
Dennis M. Newns - Yorktown Heights NY, US
Christy S. Tyberg - Mahopac NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 47/00

US Classification:

257 4, 257209, 257529, 257E2917

Abstract:

An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

US Patent:

7417315, Aug 26, 2008

Filed:

Dec 5, 2002

Appl. No.:

10/310532

Inventors:

Gareth Geoffrey Hougham - Ossining NY, US
S. Jay Chey - Ossining NY, US
James Patrick Doyle - Bronx NY, US
Xiao Hu Liu - Croton On Hudson NY, US
Christopher V. Jahnes - Upper Saddle River NJ, US
Paul Alfred Lauro - Brewster NY, US
Nancy C. LaBianca - Yalesville CT, US
Michael J. Rooks - Briarcliff Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302
B32B 5/22
G02B 26/00

US Classification:

257747, 257758, 257E2308, 257E23128, 4283179, 359291

Abstract:

A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials. ” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed. These devices have the technologically useful property of volumetrically expanding upon lowering of the device temperature below the reference or processing temperature.

US Patent:

7456098, Nov 25, 2008

Filed:

Apr 13, 2006

Appl. No.:

11/403332

Inventors:

Habib Hichri - Wappingers Falls NY, US
Xiao H. Liu - Croton On Hudson NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Conal E. Murray - Yorktown Heights NY, US
Jawahar P. Nayak - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438637, 257621, 257E21577, 257E23145

Abstract:

Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

US Patent:

7491965, Feb 17, 2009

Filed:

May 28, 2008

Appl. No.:

12/127994

Inventors:

James P. Doyle - Bronx NY, US
Bruce G. Elmegreen - Golden Bridge NY, US
Lia Krusin-Elbaum - Dobbs Ferry NY, US
Chung Hon Lam - Peekskill NY, US
Xiao Hu Liu - Briarcliff Manor NY, US
Dennis M. Newns - Yorktown Heights NY, US
Christy S. Tyberg - Mahopac NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 47/00

US Classification:

257 4, 257209, 257529, 257E2917

Abstract:

An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

US Patent:

7525161, Apr 28, 2009

Filed:

Jan 31, 2007

Appl. No.:

11/669902

Inventors:

Meikei Ieong - Wappingers Falls NY, US
Xiao Hu Liu - Briarcliff Manor NY, US
Qiqing Christine Ouyang - Yorktown Heights NY, US
Siddhartha Panda - Kanpur, IN
Haizhou Yin - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/94

US Classification:

257369, 257E27064, 257 19

Abstract:

NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.