Xiao Ming Liu

US Patent:

6353644, Mar 5, 2002

Filed:

May 3, 1999

Appl. No.:

09/303730

Inventors:

Lujing Cai - Tinton Falls NJ
Weimin Liu - Aberdeen NJ
Xiao Liu - Ocean NJ
Wenye Yang - Ocean NJ

Assignee:

Globespan, Inc. - Red Bank NJ

International Classification:

H04B 110

US Classification:

375350, 708300, 375285

Abstract:

Disclosed is a system and method for signal conditioning and equalization in the time domain, preferably in a discrete multi-tone (DMT) modem. The system preferably includes a processor operating according to operating logic stored on a memory although a dedicated logical circuit may be employed. The operating logic includes logic executing the function of a low pass filter having a predetermined cutoff frequency configured to process a digitized data signal having a first sample rate f , producing a filtered data signal at a second sample rate f. The operating logic further includes logic which executes the function of a time domain equalizer, the time domain equalizer being configured to process the filtered signal to shorten the impulse response of the channel while at the same time, the time domain equalizer down-samples the filtered signal from the second sample rate f , to a third sample rate f for further processing in the frequency domain.

US Patent:

63108968, Oct 30, 2001

Filed:

Oct 16, 1998

Appl. No.:

9/174026

Inventors:

Ehud Langberg - Wayside NJ
Weimin Liu - Aberdeen NJ
Xiao Liu - Ocean NJ
William Scholtz - Middletown NJ

Assignee:

Globespan, Inc. - Redbank NJ

International Classification:

H04J 306

US Classification:

370503

Abstract:

A system and method are disclosed for synchronizing a predetermined repeated data sequence contained in a first data signal at a first sample rate with the same predetermined repeated data sequence contained in a second data signal at a second sample rate in a data communications device. The system preferably includes a digital signal processor operating pursuant to logic stored on a memory. The logic includes synchronization logic which reduces the first sample rate to a predetermined correlation sample rate using a first decimator, resulting in a first reduced data signal. The synchronization logic also reduces the second sample rate to the same predetermined correlation sample rate using a second decimator, resulting in a second reduced data signal. Finally, the synchronization logic determines a sequence offset between the predetermined repeated data sequence contained in the first reduced data signal and the predetermined repeated data sequence contained in the second reduced data signal using a correlator. This sequence offset is used to determine a time delay that is applied to the second data signal, thereby synchronizing the predetermined repeated data sequence contained in the first and second data sequences.