Xiaochuan L Yuan

US Patent:

20080071513, Mar 20, 2008

Filed:

Sep 11, 2006

Appl. No.:

11/519381

Inventors:

Vivek Chickermane - Ithaca NY, US
James Sage - Kirkwood NY, US
Patrick Gallagher - Apalachin NY, US
Xiaochuan Yuan - Vestal NY, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G01R 27/28
G01R 31/02
G08B 21/00

US Classification:

703 15, 702118, 324537, 340635

Abstract:

In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing. By automatically partitioning the faults to remove those that cannot be excited or observed during manufacturing and testing, the testability of the device in terms of its partitions or parts will accurately reflect the power state of the logic portions of the circuit.