Yong Y Lu

US Patent:

6363007, Mar 26, 2002

Filed:

Aug 14, 2000

Appl. No.:

09/638415

Inventors:

Yong Lu - Plymouth MN
Romney R. Katti - Maple Grove MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365171

Abstract:

Methods are disclosed for writing magneto-resistive memory devices. Some of the methods help reduce peak currents during a write, while others increase the speed of the write. To reduce the peak currents, selected control signals such as selected word lines, digital lines and/or sense lines are sequentially activated, rather than activated in parallel. Because the word lines, digital lines and/or sense lines are sequentially activated, the peak currents experienced during a corresponding write may be reduced. To increase the speed of a write, the magnetization vector of the magneto-resistive bits are actively forced to be substantially parallel with the major axis of the magneto-resistive bits, rather than merely drift to that position under the forces inherent in the magneto-resistive bit.

US Patent:

6396733, May 28, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/618256

Inventors:

Yong Lu - Plymouth MN
Michael F. Dries - Chanhassen MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365207

Abstract:

A magneto-resistive memory is disclosed that includes a high-speed sense amplifier that can reliably operate at low signal levels. The sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.

US Patent:

6424561, Jul 23, 2002

Filed:

Jul 18, 2000

Appl. No.:

09/618504

Inventors:

Shaoping Li - Naperville IL
Theodore Zhu - Maple Grove MN
Anthony S. Arrott - Washington DC
Harry Liu - Plymouth MN
William L. Larson - Eden Prairie MN
Yong Lu - Plymouth MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365171, 365173

Abstract:

MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

US Patent:

6424564, Jul 23, 2002

Filed:

Sep 26, 2001

Appl. No.:

09/964217

Inventors:

Shaoping Li - Naperville IL
Theodore Zhu - Maple Grove MN
Anthony S. Arrott - Washington DC
Harry Liu - Plymouth MN
William L. Larson - Eden Prairie MN
Yong Lu - Plymouth MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365171, 365173, 365 66

Abstract:

MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

US Patent:

6487111, Nov 26, 2002

Filed:

Oct 31, 2001

Appl. No.:

10/002071

Inventors:

Yong Lu - Plymouth MN
Michael F. Dries - Chanhassen MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158

Abstract:

A magneto-resistive memory is disclosed that includes a high-speed sense amplifier that can reliably operate at low signal levels. The sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.

US Patent:

6493258, Dec 10, 2002

Filed:

Jul 18, 2000

Appl. No.:

09/618237

Inventors:

Yong Lu - Plymouth MN
Theodore Zhu - Maple Grove MN
Romney R. Katti - Maple Grove MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365157, 365171, 365173

Abstract:

A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.

US Patent:

6522574, Feb 18, 2003

Filed:

Sep 25, 2001

Appl. No.:

09/964218

Inventors:

Shaoping Li - Naperville IL
Theodore Zhu - Maple Grove MN
Anthony S. Arrott - Washington DC
Harry Liu - Plymouth MN
William L. Larson - Eden Prairie MN
Yong Lu - Plymouth MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365171, 365173, 365 66

Abstract:

MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

US Patent:

6522576, Feb 18, 2003

Filed:

Nov 14, 2001

Appl. No.:

09/992213

Inventors:

Yong Lu - Plymouth MN
Theodore Zhu - Maple Grove MN
Romney R. Katti - Maple Grove MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1100

US Classification:

365158, 365171, 365173

Abstract:

A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.

Address:

7115 Tralee Dr, Minneapolis, MN 55439

VIN:

JM1CR293490348764

Make:

MAZDA

Model:

MAZDA5

Year:

2009