Yu L Lu

US Patent:

7123507, Oct 17, 2006

Filed:

Aug 19, 2004

Appl. No.:

10/922298

Inventors:

David W. Abraham - Croton NY, US
Yu Lu - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 19/02

US Classification:

365158, 365 55, 365157

Abstract:

A method, information processing system and computer readable medium for transferring data between applications on a computer is disclosed. The method includes selecting data from a first application and selecting a copy-to command for copying the data selected from the first application. The method further includes selecting a second application as a destination for the data selected. The method further includes selecting a location in the second application for inserting the data selected.

US Patent:

8638587, Jan 28, 2014

Filed:

Aug 2, 2013

Appl. No.:

13/957937

Inventors:

William J. Gallagher - Ardsley NY, US
Yu Lu - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 19/00

US Classification:

365 81, 365148, 365158, 365173, 977933

Abstract:

In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.

US Patent:

20180192770, Jul 12, 2018

Filed:

Feb 16, 2017

Appl. No.:

15/434327

Inventors:

- Ontario CA, US
YU SHENG LU - ONTARIO CA, US

International Classification:

A47B 23/04
A47B 23/06

Abstract:

A computer support frame structure includes two supports each having a bottom section. The bottom sections transversely extend on the same horizontal face. A middle support section is connected with one end of the bottom section. The middle support section obliquely upward extends from the end of the bottom section. A rest section further transversely extends from an upper end of the middle support section in a direction approximately in parallel to the direction of the bottom section. An upper connection member is secured between the middle sections of the middle support sections. A lower connection member is secured between the middle sections of the bottom sections. The upper and lower connection members and the two supports together forma four-bar linkage to enhance the structural stability, whereby a computer can be securely placed on the rest sections.

US Patent:

20150228753, Aug 13, 2015

Filed:

Apr 28, 2015

Appl. No.:

14/698206

Inventors:

- Armonk NY, US
SHU-JEN HAN - CORTLANDT MANOR NY, US
YU LU - HOPEWELL JUNCTION NY, US
KEITH KWONG HON WONG - NEW YORK NY, US

International Classification:

H01L 29/66
H01L 29/423
H01L 21/306
H01L 21/04
H01L 29/16
H01L 21/02

Abstract:

Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer.

US Patent:

20150187764, Jul 2, 2015

Filed:

Mar 10, 2015

Appl. No.:

14/643224

Inventors:

- Armonk NY, US
Shu-Jen Han - Cortlandt Manor NY, US
Yu Lu - Hopewell Junction NY, US
Keith Kwong Hon Wong - New York NY, US

International Classification:

H01L 27/088

Abstract:

A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions.

US Patent:

20140332860, Nov 13, 2014

Filed:

May 9, 2013

Appl. No.:

13/890849

Inventors:

- Armonk NY, US
Shu-Jen Han - Cortlandt Manor NY, US
Yu Lu - Hopewell Junction NY, US
Keith Kwong Hon Wong - New York NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/66
H01L 29/78

US Classification:

257288, 438299

Abstract:

Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions.

US Patent:

20140332862, Nov 13, 2014

Filed:

Aug 15, 2013

Appl. No.:

13/968101

Inventors:

- Armonk NY, US
Shu-Jen Han - Cortlandt Manor NY, US
Yu Lu - Hopewell Junction NY, US
Keith Kwong Hon Wong - New York NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78

US Classification:

257288

Abstract:

Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.

US Patent:

20140312412, Oct 23, 2014

Filed:

Apr 17, 2013

Appl. No.:

13/864760

Inventors:

- ARMONK NY, US
SHU-JEN HAN - CORTLANDT MANOR NY, US
YU LU - HOPEWELL JUNCTION NY, US
KEITH KWONG HON WONG - NEW YORK NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 29/78
H01L 29/66

US Classification:

257330, 438270

Abstract:

Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.