Yu Ying Lu

US Patent:

20170104153, Apr 13, 2017

Filed:

Dec 22, 2016

Appl. No.:

15/389322

Inventors:

- San Diego CA, US
Matthias Georg Gottwald - Heverlee, BE
Mustafa Badaroglu - Leuven, BE
Jimmy Kan - San Diego CA, US
Kangho Lee - San Diego CA, US
Yu Lu - San Diego CA, US
Chando Park - San Diego CA, US

International Classification:

H01L 43/12
H01L 43/02
H01L 43/08
H01L 27/22

Abstract:

A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

US Patent:

20170047510, Feb 16, 2017

Filed:

Aug 12, 2015

Appl. No.:

14/824507

Inventors:

- San Diego CA, US
Yu Lu - San Diego CA, US
Chando Park - Irvine CA, US
Seung Hyuk Kang - San Diego CA, US

International Classification:

H01L 43/12
H01L 43/08
H01L 27/22
H01L 43/02

Abstract:

Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

US Patent:

20160372518, Dec 22, 2016

Filed:

Jun 19, 2015

Appl. No.:

14/744984

Inventors:

- San Diego CA, US
Xiaochun Zhu - San Diego CA, US
Yu Lu - San Diego CA, US

International Classification:

H01L 27/22
H01L 43/12
H01L 43/08
G11C 11/16
H01L 43/02

Abstract:

A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor.

US Patent:

20160329488, Nov 10, 2016

Filed:

Jul 18, 2016

Appl. No.:

15/213384

Inventors:

- San Diego CA, US
Yu LU - San Diego CA, US
Seung Hyuk KANG - San Diego CA, US

International Classification:

H01L 43/02
H01L 43/12
H01L 43/08

Abstract:

A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

US Patent:

20160315248, Oct 27, 2016

Filed:

Sep 22, 2015

Appl. No.:

14/860931

Inventors:

- San Diego CA, US
Yu Lu - San Diego CA, US
Chando Park - Irvine CA, US
Seung Hyuk Kang - San Diego CA, US

International Classification:

H01L 43/02
H01L 43/12
H01L 43/08

Abstract:

Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

US Patent:

20160254446, Sep 1, 2016

Filed:

May 6, 2016

Appl. No.:

15/149004

Inventors:

- San Diego CA, US
Yu LU - San Diego CA, US

International Classification:

H01L 43/12
H01L 43/02
G11C 11/16
H01L 43/10
H01L 43/08
H01L 27/22

Abstract:

A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar.

US Patent:

20160225817, Aug 4, 2016

Filed:

Jan 29, 2015

Appl. No.:

14/609169

Inventors:

- San Diego CA, US
Matthias Georg Gottwald - Heverlee, BE
Mustafa Badaroglu - Leuven, BE
Jimmy Kan - San Diego CA, US
Kangho Lee - San Diego CA, US
Yu Lu - San Diego CA, US
Chando Park - San Diego CA, US

International Classification:

H01L 27/22
H01L 43/08
H01L 43/12
H01L 43/02

Abstract:

A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

US Patent:

20160172456, Jun 16, 2016

Filed:

Dec 11, 2014

Appl. No.:

14/567925

Inventors:

- San Diego CA, US
John Jianhong Zhu - San Diego CA, US
Jeffrey Junhao Xu - San Diego CA, US
Bin Yang - San Diego CA, US
Jun Yuan - San Diego CA, US
Yu Lu - San Diego CA, US

International Classification:

H01L 29/417
H01L 21/283

Abstract:

A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.