Square
Software Engineer
Dartmouth College Sep 2011 - Apr 2016
Research Assistant
Te Connectivity May 2014 - Aug 2014
Internship
Education:
Georgia Institute of Technology 2016 - 2018
Masters, Computer Science
Dartmouth College 2011 - 2016
Doctorates, Doctor of Philosophy, Philosophy
Dartmouth College 2011 - 2015
University of Florida 2009 - 2011
Master of Science, Masters, Engineering
Tsinghua University 2005 - 2009
Bachelor of Engineering, Bachelors, Materials Science
Hunan Normal University
Dartmouth College
Skills:
Matlab Python Data Analysis C++ Go Research Statistics Ruby on Rails C R Java Modeling Javascript Latex
Certifications:
Cfa Level 1 Lean Six Sigma Green Belt (Icgb) Engineering Management Certification Fundamentals (Emcp)
Jawahar Jain - Santa Clara CA Yuan Lu - Pittsburgh PA
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 1710
US Classification:
703 2, 716 3, 716 7
Abstract:
A system and method for determining variable orders for decision diagrams. The variable orders are determined by sampling subspaces of a Boolean space representing a function or circuit. The subspaces are formed in a variety of ways, including through the use of abstraction, decomposition, partial assignments, and circuit subspaces.
Design Verification For A Switching Network Logic Using Formal Techniques
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.
Yuan Lu - San Jose CA, US Yunshan Zhu - Cupertino CA, US
International Classification:
G06F 17/50
US Classification:
716136
Abstract:
One embodiment of the present invention provides a method that automatically generates assertions of a hardware design. The method includes accessing a trace and a set of predicates of the hardware design. Then, the trace is projected over the set of predicates to generate a second trace. Then, a new set of states of the second trace is computed and the result is represented as a logical formula. The formula is reduced by logic optimization techniques. And finally, a set of logical consequences of the logic formula is produced and each logical consequence is enumerated as an assertion.
Systems And Methods For Generating Predicates And Assertions
Yuan Lu - San Jose CA, US Yunshan Zhu - Cupertino CA, US
Assignee:
NextOp Software, Inc. - San Jose CA
International Classification:
G06N 5/00
US Classification:
706 12, 706 45
Abstract:
Systems and methods for deriving a predicate by constructing a logic formula from information recorded during test execution, optimizing the logic formula and computing the logical implication of the optimized logic formula. Systems and methods for deriving an assertion from a logical implication by substituting each predicate in the logical implication with corresponding design elements from a hardware design description, inserting the design elements into a target template, inserting a context-sensitive input of the target template based on design elements in the hardware design description and creating an instance name for an instantiation of the target template. Systems and methods for generating a set of clauses that are implied by a disjunctive normal formula of a set of cubes.
Jinho Park - San Jose CA, US Yuan Lu - Sunnyvale CA, US Li Lin - Saratoga CA, US
Assignee:
Marvell World Trade Ltd. - Hamilton
International Classification:
H03F 3/26
US Classification:
330267, 330264
Abstract:
The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit.
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.
A method and apparatus for managing memory according to several embodiments of the invention. According to embodiments, the invention includes providing a memory including a plurality of memory locations configured to store data, providing a memory address pool having a plurality of available memory addresses and providing a cell free address pool (CFAP), including a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool.
Systems And Methods For Generating Predicates And Assertions
Yuan Lu - San Jose CA, US Yunshan Zhu - Cupertino CA, US
International Classification:
G06F 15/18 G06N 5/02
US Classification:
706 12, 706 56
Abstract:
Systems and methods for deriving a predicate by constructing a logic formula from information recorded during test execution, optimizing the logic formula and computing the logical implication of the optimized logic formula. Systems and methods for deriving an assertion from a logical implication by substituting each predicate in the logical implication with corresponding design elements from a hardware design description, inserting the design elements into a target template, inserting a context-sensitive input of the target template based on design elements in the hardware design description and creating an instance name for an instantiation of the target template. Systems and methods for generating a set of clauses that are implied by a disjunctive normal formula of a set of cubes.
Dr. Lu graduated from the Shanghai Med Univ, Shanghai First Med Univ, Shanghai, China in 1987. He works in Fayetteville, NC and 1 other location and specializes in Nephrology. Dr. Lu is affiliated with Cape Fear Valley Medical Center, Highsmith-Rainey Specialty Hospital and Southeastern Regional Medical Center.
National Taiwan Normal University - Honours Bachelor of Music in Bassoon Performance, Taipei National University of the Arts - Honours Bachelor of Music in Bassoon Performance, The Affiliated Senior High School of National Taiwan Normal University
Yuan Lu
Lived:
烟台 北京 无锡 Madison, WI Kent, WA Schaumburg, IL
Yuan Lu
Education:
Harvard University - Public Health
Yuan Lu
About:
Windows Live, please return my space!
Yuan Lu
Yuan Lu
Yuan Lu
Yuan Lu
Flickr
Youtube
2009 Yonex/OCBC US Open - Day 2 - Part 13
Day 2 Highlights Howard BACH & Tony GUNAWAN vs. Alvin LAU & Kailai ZHA...
Category:
People & Blogs
Uploaded:
10 Jul, 2009
Duration:
10m 37s
MailDefender Operation Illustration, by BioDe...
Be Safe, Be Sure. Operation Illustrations. MailDefender by BioDefense ...
Category:
Science & Technology
Uploaded:
02 Apr, 2009
Duration:
2m 35s
C Star 2009 Stage 2 Group1A
UK C-Star 2009 Sining Competition Stage 2 c-star.c... Video Time Line...
Category:
Entertainment
Uploaded:
16 Apr, 2009
Duration:
8m 39s
2-Lu,Style chen xin yi hun yuan
www.xingwutj.com E-ma... 85681722 ...
Category:
Sports
Uploaded:
31 Oct, 2008
Duration:
9m 56s
Yuan Gong Quan San Lu
road 3 of the 12 basic roads in the yuan gong quan ( ape skill boxing)...
Category:
Sports
Uploaded:
15 Oct, 2010
Duration:
32s
Yuan Shao - Dynasty Warriors 5 Xtreme Legends...
PART1 Dynasty Warriors 5 Xtreme Legends Chaos Mode Battle of Guan Du (...