Jun 2014 to 2000 Staff accountantZHENGHUI Accounting Firm Weihai, CN Jun 2012 to Jul 2012 Intern AccountantDISHANG KENNY Weihai, CN Nov 2011 to Dec 2011 Part time worker
Education:
The University of Texas at Dallas Dallas, TX May 2014 Master of Science in AccountingShanghai University 2012 Bachelor of Business
Skills:
CPA candidate, GP
Name / Title
Company / Classification
Phones & Addresses
Yuan Xu President
MODERN ADVERTISING CORP
310 S California STE D, San Gabriel, CA 91776
Us Patents
P Channel Radhard Device With Boron Diffused P-Type Polysilicon Gate
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 21/336
US Classification:
257402, 257E21625
Abstract:
A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between −2V to −5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.
P Channel Radhard Device With Boron Diffused P-Type Polysilicon Gate
Milton J. Boden - Redondo Beach CA Yuan Xu - El Segundo CA
Assignee:
International Rectifier Corp. - El Segundo CA
International Classification:
H01L 21332
US Classification:
438137
Abstract:
A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.