Zarir Barjor Sarkari

US Patent:

6345378, Feb 5, 2002

Filed:

Mar 23, 1995

Appl. No.:

08/409191

Inventors:

Christian Joly - Palo Alto CA
Zarir Sarkari - San Jose CA
Ravichandran Ramachandran - Sunnyvale CA
Sarika Agrawal - Santa Clara CA
Sanjay Adkar - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 2, 716 3

Abstract:

A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customers design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider. Since all the information that is needed by a synthesizer is available in the synthesis shell in netlist form, the shell is extremely accurate. The synthesis shell as mentioned above comprises a gate level description which is a subset of the synthesized block.

US Patent:

56442513, Jul 1, 1997

Filed:

Sep 26, 1995

Appl. No.:

8/533688

Inventors:

Michael Colwell - Livermore CA
Rochit Rajsuman - San Jose CA
Ray Abrishami - Los Altos CA
Zarir B. Sarkari - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 1900

US Classification:

326 16

Abstract:

An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

US Patent:

58448187, Dec 1, 1998

Filed:

May 10, 1996

Appl. No.:

8/627823

Inventors:

Dan Kochpatcharin - Union City CA
Zarir B. Sarkari - San Jose CA
Christian Joly - Palo Alto CA
Allen Wu - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 9455

US Classification:

364578

Abstract:

A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.

US Patent:

56708904, Sep 23, 1997

Filed:

Sep 26, 1995

Appl. No.:

8/533704

Inventors:

Michael Colwell - Livermore CA
Rochit Rajsuman - San Jose CA
Ray Abrishami - Los Altos CA
Zarir B. Sarkari - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

324765

Abstract:

An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

US Patent:

56444982, Jul 1, 1997

Filed:

Jan 25, 1995

Appl. No.:

8/377844

Inventors:

Christian Joly - Palo Alto CA
Francois Ducaroir - San Francisco CA
Zarir Sarkari - San Jose CA
Allen Wu - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1500

US Classification:

364489

Abstract:

Gate level netlists used for timing analysis in integrated circuit design are reduced using a timing shell generator while preserving critical information for timing analysis. After verification of timings, the gate level netlist is convened into a shell containing block boundary information. The function of the shell generator is to delete internal cells meeting a set of criteria. The result is a shell netlist containing a subset of the original netlist. Thus, the design cycle time involved and computing time and resources needed in ASIC development for chips using circuits represented by timing shell netlists are decreased by substituting design verification at the top level of large hierarchical netlists or large flat netlists by bottom up verification procedures using timing shells.