Ashwin Rao

US Patent:

7499368, Mar 3, 2009

Filed:

Feb 7, 2005

Appl. No.:

11/052371

Inventors:

Ashwin K. Rao - Allen TX, US
Sang-Won Song - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 8/00

US Classification:

3652331, 36518905, 36523313

Abstract:

A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.