Craig D Wilson

US Patent:

7411231, Aug 12, 2008

Filed:

Dec 1, 2006

Appl. No.:

11/566099

Inventors:

Craig Wilson - Livermore CA, US
Derek Bowers - Los Altos Hills CA, US
Gregory K. Cestra - Pleasanton CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01L 29/80
H01L 21/337

US Classification:

257256, 257272, 257E29314, 438186, 438194

Abstract:

The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

US Patent:

7511939, Mar 31, 2009

Filed:

Aug 24, 2007

Appl. No.:

11/895339

Inventors:

Craig Wilson - Livermore CA, US
Michael Dunbar - San Jose CA, US
Derek Bowers - Los Altos Hills CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01G 4/228

US Classification:

3613062, 3613061, 3613063, 3613014, 361311, 361313, 438253, 438620, 438622, 257295, 257296

Abstract:

A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

US Patent:

7609144, Oct 27, 2009

Filed:

Dec 8, 2006

Appl. No.:

11/608668

Inventors:

Michael Lee - High Wycombe, GB
Steven Wright - Northchurch, GB
Philip Judge - Richmond, GB
Craig Wilson - Livermore CA, US
Gregory Cestra - Pleasanton CA, US
Derek Bowers - Los Altos Hills CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H01C 1/012

US Classification:

338308, 338309, 296101

Abstract:

A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a ρ of at least 0. 02 Ω-cm (typically 0. 02-1. 0 Ω-cm), and a TCR of less than 1000 ppm/ C. (typically less than 300 ppm/ C. ). A sheet resistance of at least 20 kΩ/□ may also be obtained. The resulting thin film is preferably at least 200 thick, to reduce surface scattering conduction currents.