Jose S Cavazos

US Patent:

20040124899, Jul 1, 2004

Filed:

Feb 12, 2003

Appl. No.:

10/344488

Inventors:

Jose Cavazos - Houston TX, US
Robert Simie - Seabrook TX, US

International Classification:

H03K003/02

US Classification:

327/199000

Abstract:

A synchronizer eliminates metastability due to violation of either the setup time or the hold time of a circuit. The input of a first flip-flop () is tied to a constant logic level (VDD or ground). The first flip-flop receives an asynchronous signal into the reset (preset or clear) input of the flip-flop. No violation of the setup or hold times of the flip-flop can occur. The second flip-flop () receives the output of the first flip-flop as its clock input. The second flip-flop () is configured as a toggler. The second flip-flop produces a synchronized partial signal () of the original asynchronous signal (). Third and fourth flip-flops () may similarly be configured to produce a second synchronized partial signal () of the asynchronous signal recovery and may prevent runt pulses from being received by the flip-flops.

Address:

1602 Brahman St, Mercedes, TX 78570

VIN:

5TFRM5F14BX031268

Make:

TOYOTA

Model:

TUNDRA

Year:

2011