Young Taek Park

Address:

33020 10 Ave SW UNIT H, Federal Way, WA 98023

Phone:

3608958591

VIN:

JTHCL5EF2C5013711

Make:

LEXUS

Model:

LS 460

Year:

2012

US Patent:

20120142105, Jun 7, 2012

Filed:

Oct 3, 2011

Appl. No.:

13/251960

Inventors:

Sung-Yong Harrison Yoon - Lake Oswego OR, US
Young Chul Park - Beaverton OR, US
Amy McDonald - Oregon City OR, US
Camille Pierre Dubois - Milwaukie OR, US
Sonia Lall - Portland OR, US

Assignee:

DianaPlantSciences, Inc. - Portland OR

International Classification:

C12N 5/00

US Classification:

435410

Abstract:

A method of preparing cocoa oligomeric procyanidins from cocoa cell cultures grown in the presence of monosaccharide can increase production of procyanidins as follows: culturing cells sufficient to result in production of cocoa oligomeric procyanidins at a first rate; and introducing a monosaccharide to the cells sufficient for inducing the cells to produce the cocoa oligomeric procyanidins at a second rate that his higher than the first rate. The method can further include extracting the cocoa oligomeric procyanidins from the cells, and such extracting can occur between 1 day to 21 days after introduction of the monosaccharide. Optionally, the monosaccharide can be introduced in an amount about 0.5% to about to about 20% by volume of the culture medium. The monosaccharide can be glucose, sucrose, fructose, or the like. The monosaccharide can be introduced during or after a last phase of an exponential growth state.

US Patent:

20160204787, Jul 14, 2016

Filed:

Sep 26, 2013

Appl. No.:

14/127963

Inventors:

- Santa Clara CA, US
Mohamed A. ABDELSALAM - Giza, EG
Mamdouh O. ABD EL-MEJEED - Alexandria, EG
Nasser A. KURD - Portland OR, US
Mark ELZINGA - El Dorado CA, US
Young Min PARK - Folsom CA, US
Jagannadha R. RAPETA - Folsom CA, US
Surya MUSUNURI - Folsom CA, US

International Classification:

H03L 7/10
G04F 10/00
H03L 7/099

Abstract:

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.