Xiao Ling Luo

US Patent:

7345912, Mar 18, 2008

Filed:

Jun 1, 2006

Appl. No.:

11/446391

Inventors:

Xiao Luo - Cupertino CA, US
Eugene Youjun Chen - Fremont CA, US
Lien-Chang Wang - Fremont CA, US
Yiming Huai - Pleasanton CA, US

Assignee:

Grandis, Inc. - Milpitas CA
Renesas Technology Corp. - Tokyo

International Classification:

G11C 11/00

US Classification:

365158, 365157

Abstract:

A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

US Patent:

7379327, May 27, 2008

Filed:

Jun 26, 2006

Appl. No.:

11/476171

Inventors:

Eugene Youjun Chen - Fremont CA, US
Yiming Huai - Pleasanton CA, US
Alex Fischer Panchula - San Carlos CA, US
Lien-Chang Wang - Fremont CA, US
Xiao Luo - Cupertino CA, US

Assignee:

Grandis, Inc. - Milpitas CA
Renesas Technology Corp. - Tokyo

International Classification:

G11C 11/00

US Classification:

365158, 365171, 365173

Abstract:

A method and system for providing a magnetic memory. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer. The magnetic memory is configured such that either the read current(s) flow from the free layer(s) to the dominant spacer if the maximum low resistance state read current divided by the minimum low resistance state write current is greater than the maximum high resistance state read current divided by the minimum high resistance state write current or the read current(s) flow from the dominant spacer to the free layer(s) if the maximum low resistance state read current divided by the minimum low resistance state write current is less than the maximum high resistance state read current divided by the minimum high resistance state write current.

US Patent:

7623369, Nov 24, 2009

Filed:

Feb 13, 2008

Appl. No.:

12/030541

Inventors:

Xiao Luo - Cupertino CA, US
Eugene Chen - Fremont CA, US
Lien-Chang Wang - Fremont CA, US
Yiming Huai - Pleasanton CA, US

Assignee:

Grandis, Inc. - Milpitas CA
Renesas Technology Corp. - Tokyo

International Classification:

G11C 16/04

US Classification:

365158, 365173

Abstract:

A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

US Patent:

7764536, Jul 27, 2010

Filed:

Aug 7, 2007

Appl. No.:

11/834917

Inventors:

Xiao Luo - Cupertino CA, US
David Chang-Cheng Yu - Pleasanton CA, US

Assignee:

Grandis, Inc. - Milpitas CA
Renesas Technology Corp. - Tokyo

International Classification:

G11C 11/00

US Classification:

365158, 365157, 365148, 365171, 365173, 365 97

Abstract:

A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disables at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.

US Patent:

20070279967, Dec 6, 2007

Filed:

May 18, 2006

Appl. No.:

11/436446

Inventors:

Xiao Luo - Cupertino CA, US
Lien-Chang Wang - Fremont CA, US

International Classification:

H01L 29/76
H01L 29/94
G11C 11/00
G11C 11/14
H01L 31/00

US Classification:

365158, 365171, 257401

Abstract:

A method and system for providing and using a magnetic storage cell and magnetic memory is described. The method and system include providing a magnetic element and providing a selection device. The magnetic element is programmable to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction. The selection device is connected with the magnetic element. The selection device includes a gate having an aperture therein. The selection device is configured such that the first write current and second write current are provided to the magnetic element across the aperture.

US Patent:

20120246507, Sep 27, 2012

Filed:

Mar 22, 2012

Appl. No.:

13/427465

Inventors:

Xiao Luo - Cupertino CA, US
Adrian E. Ong - Pleasanton CA, US

Assignee:

GRANDIS INC. - Milpitas CA

International Classification:

G06F 11/07

US Classification:

714 2, 714 54, 714E11023, 714E11024

Abstract:

A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.

Address:

223 Miramar Ave, San Francisco, CA 94112

VIN:

4JGBB5GB2AA575117

Make:

MERCEDES-BENZ

Model:

M-CLASS

Year:

2010