Zhuoxiang Ren - Santa Clara CA, US Weidong Zhang - San Jose CA, US Jim Falbo - Tualatin OR, US
International Classification:
G06F 17/50
US Classification:
716 21, 716 4, 716 19
Abstract:
A system for calculating electrical properties of features to be created in an integrated circuit. All or a portion of a desired layout design is corrected for photolithographic or other process distortions using one or more resolution enhancement techniques. A simulated layout image of a corrected layout is used as an input to a field solver program that calculates the electrical properties of the features as they will be printed on a wafer.