Vincent W Leung

US Patent:

6732308, May 4, 2004

Filed:

Sep 19, 2000

Appl. No.:

09/664819

Inventors:

Vincent C. Leung - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3128

US Classification:

714724, 36518533, 711103

Abstract:

The present invention discloses an embedded and test mode timer circuit that is used to perform operations in an embedded mode and a plurality of test modes in a memory device. When the memory device is operating in the embedded mode, the embedded and test mode timer circuit is activated to automatically direct at least one logic circuit to execute logic tasks at predetermined times. When the memory device is operating in a test mode, the embedded and test mode timer circuit is activated to automatically direct a portion of the logic circuits to execute logic tasks at predetermined times and the remaining portion of the logic circuit are manually directed.

US Patent:

7557617, Jul 7, 2009

Filed:

Jan 3, 2007

Appl. No.:

11/649618

Inventors:

Vincent Leung - San Francisco CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/094
G11C 8/00

US Classification:

326105, 326113

Abstract:

A digital decoder is provided that produces true and complementary output signals. The digital decoder may be formed from n-channel and p-channel metal-oxide-semiconductor transistors. The digital decoder produces four true outputs and four complementary outputs from two inputs. A first of the true outputs and a first of the complementary outputs are provided using a NOR gate and an inverter. A NAND gate and an inverter are used to provide a second of the true outputs and a second of the complementary outputs. Third and fourth complementary outputs are produced using first and second logic circuits. The first and second logic circuits are powered using only a positive power supply voltage. Third and fourth true outputs are produced using third and fourth logic circuits. The third and fourth logic circuits are powered using only a ground power supply voltage. The logic circuits each include an n-channel and p-channel transistor pair.

US Patent:

7598769, Oct 6, 2009

Filed:

Feb 15, 2007

Appl. No.:

11/675590

Inventors:

Vincent Leung - San Francisco CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 40, 326 46

Abstract:

A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2tri-state buffers coupled to receive the 2configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2tri-state buffers so that one or more of the 2configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.

US Patent:

58525769, Dec 22, 1998

Filed:

Oct 6, 1997

Appl. No.:

8/944904

Inventors:

Binh Quang Le - Mountain View CA
Shane Charles Hollmer - San Jose CA
Shoichi Kawamura - Sunnyvale CA
Michael Shingche Chung - San Jose CA
Vincent C. Leung - Mountain View CA
Masaru Yano - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa-ken

International Classification:

G11C 1300

US Classification:

36518533

Abstract:

Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them.